Display device

1 . A display device, comprising a display panel, the display panel comprising driving circuits in a plurality of cascaded stages, each of the driving circuits comprising a gate driving signal sub-circuit, an initialization signal sub-circuit, and a reference signal sub-circuit;

wherein the gate driving signal sub-circuit, the initialization signal sub-circuit, and the reference signal sub-circuit each comprises a plurality of oxide semiconductor transistors, a bottom gate of each of at least a part of the oxide semiconductor transistors in the gate driving signal sub-circuit is electrically connected to a potential control signal input terminal, a bottom gate of each of at least a part of the oxide semiconductor transistors in the initialization signal sub-circuit is electrically connected to the potential control signal input terminal, and a bottom gate of each of at least a part of the oxide semiconductor transistors in the reference signal sub-circuit is electrically connected to the potential control signal input terminal.

2 . The display device according to claim 1 , wherein bottom gates of at least three of the oxide semiconductor transistors in the gate driving signal sub-circuit are electrically connected to the potential control signal input terminal.

3 . The display device according to claim 1 , wherein the gate driving signal sub-circuit comprises:

a first transistor, wherein a top gate of the first transistor is electrically connected to a subsequent-stage initialization signal input terminal, a drain of the first transistor is electrically connected to a first node, a source of the first transistor is electrically connected to a first low-level power signal input terminal, and a bottom gate of the first transistor is electrically connected to the potential control signal input terminal;

a second transistor, wherein a top gate of the second transistor is electrically connected to a start signal input terminal, a drain of the second transistor is electrically connected to the first node, a source of the second transistor is electrically connected to the first low-level power signal input terminal, and a bottom gate of the second transistor is electrically connected to the potential control signal input terminal; and

a third transistor, wherein a source of the third transistor is electrically connected to the first low-level power signal input terminal, a drain of the third transistor is electrically connected to the first node, a top gate of the third transistor is electrically connected to a second node, and a bottom gate of the third transistor is electrically connected to the potential control signal input terminal.

4 . The display device according to claim 3 , wherein the gate driving signal sub-circuit further comprises:

a fourth transistor, wherein a top gate of the fourth transistor is electrically connected to a preceding-stage initialization signal input terminal, a source of the fourth transistor is electrically connected to a high-level power signal input terminal, and a drain of the fourth transistor is electrically connected to the first node;

a fifth transistor, wherein a source of the fifth transistor is electrically connected to a clock signal input terminal, a top gate of the fifth transistor is electrically connected to the first node, and a drain of the fifth transistor is electrically connected to a gate driving signal output terminal;

a sixth transistor, wherein a top gate of the sixth transistor is electrically connected to the second node, a source of the sixth transistor is electrically connected to the first low-level power signal input terminal, and a drain of the sixth transistor is electrically connected to the gate driving signal output terminal;

a seventh transistor, wherein a top gate and a source of the seventh transistor are both electrically connected to the high-level power signal input terminal;

an eighth transistor, wherein a top gate of the eighth transistor is electrically connected to the high-level power signal input terminal, a source of the eighth transistor is electrically connected to a drain of the seventh transistor, and a drain of the eighth transistor is electrically connected to the second node;

a ninth transistor, wherein a top gate of the ninth transistor is electrically connected to the first node, a drain of the ninth transistor is electrically connected to the second node, and a source of the ninth transistor is electrically connected to the first low-level power signal input terminal;

a tenth transistor, wherein a top gate of the tenth transistor is electrically connected to the preceding-stage initialization signal input terminal, a drain of the tenth transistor is electrically connected to the second node, and a source of the tenth transistor is electrically connected to the first low-level power signal input terminal; and

a first capacitor, wherein a first plate of the first capacitor is electrically connected to the first node, and a second plate of the first capacitor is electrically connected to the gate driving signal output terminal.

5 . The display device according to claim 1 , wherein bottom gates of at least three of the oxide semiconductor transistors in the initialization signal sub-circuit are electrically connected to the potential control signal input terminal.

6 . The display device according to claim 1 , wherein the initialization signal sub-circuit comprises:

an eleventh transistor, wherein a top gate of the eleventh transistor is electrically connected to a subsequent-stage initialization signal input terminal, a drain of the eleventh transistor is electrically connected to a third node, a source of the eleventh transistor is electrically connected to a first low-level power signal input terminal, and a bottom gate of the eleventh transistor is electrically connected to the potential control signal input terminal;

a twelfth transistor, wherein a top gate of the twelfth transistor is electrically connected to a start signal input terminal, a drain of the twelfth transistor is electrically connected to the third node, a source of the twelfth transistor is electrically connected to the first low-level power signal input terminal, and a bottom gate of the twelfth transistor is electrically connected to the potential control signal input terminal; and

a thirteenth transistor, wherein a source of the thirteenth transistor is electrically connected to the first low-level power signal input terminal, a top gate of the thirteenth transistor is electrically connected to a fourth node, a drain of the thirteenth transistor is electrically connected to the third node, and a bottom gate of the thirteenth transistor is electrically connected to the potential control signal input terminal.

7 . The display device of claim 6 , wherein the initialization signal sub-circuit further comprises:

a fourteenth transistor, wherein a top gate of the fourteenth transistor is electrically connected to the preceding-stage initialization signal input terminal, a source of the fourteenth transistor is electrically connected to a high-level power signal input terminal, and a drain of the fourteenth transistor is electrically connected to the third node;

a fifteenth transistor, wherein a source of the fifteenth transistor is electrically connected to a clock signal input terminal, a top gate of the fifteenth transistor is electrically connected to the third node, and a drain of the fifteenth transistor is electrically connected to an initialization signal output terminal;

a sixteenth transistor, wherein a top gate of the sixteenth transistor is electrically connected to the fourth node, a source of the sixteenth transistor is electrically connected to the first low-level power signal input terminal, and a drain of the sixteenth transistor is electrically connected to the initialization signal output terminal;

a seventeenth transistor, wherein a top gate and a source of the seventeenth transistor are both electrically connected to the high-level power signal input terminal;

an eighteenth transistor, wherein a top gate of the eighteenth transistor is electrically connected to the high-level power signal input terminal, a source of the eighteenth transistor is electrically connected to a drain of the seventeenth transistor, and a drain of the eighteenth transistor is electrically connected to the fourth node;

a nineteenth transistor, wherein a top gate of the nineteenth transistor is electrically connected to the third node, a drain of the nineteenth transistor is electrically connected to the fourth node, and a source of the nineteenth transistor is electrically connected to the first low-level power signal input terminal;

a twentieth transistor, wherein a top gate of the twentieth transistor is electrically connected to the preceding-stage initialization signal input terminal, a drain of the twentieth transistor is electrically connected to the fourth node, and a source of the twentieth transistor is electrically connected to the first low-level power signal input terminal; and

a second capacitor, wherein a first plate of the second capacitor is electrically connected to the third node, and a second plate of the second capacitor is electrically connected to the initialization signal output terminal.

8 . The display device according to claim 1 , wherein bottom gates of at least four of the oxide semiconductor transistors in the reference signal sub-circuit are electrically connected to the potential control signal input terminal.

9 . The display device according to claim 1 , wherein the reference signal sub-circuit comprises:

a twenty-first transistor, wherein a top gate of the twenty-first transistor is electrically connected to a current-stage gate driving signal output terminal, a source of the twenty-first transistor is electrically connected to a first low-level power signal input terminal, a drain of the twenty-first transistor is electrically connected to a fifth node, and a bottom gate of the twenty-first transistor is electrically connected to the potential control signal input terminal;

a twenty-second transistor, wherein a top gate of the twenty-second transistor is electrically connected to the current-stage gate driving signal output terminal, a drain of the twenty-second transistor is electrically connected to a seventh node, a source of the twenty-second transistor is electrically connected to the current-stage gate driving signal output terminal, and a bottom gate of the twenty-second transistor is electrically connected to the potential control signal input terminal;

a twenty-third transistor, wherein a top gate of the twenty-third transistor is electrically connected to a current-stage initialization signal input terminal, a drain of the twenty-third transistor is electrically connected to the seventh node, a source of the twenty-third transistor is electrically connected to the first low-level power signal input terminal, and a bottom gate of the twenty-third transistor is electrically connected to the potential control signal input terminal; and

a twenty-fourth transistor, wherein a source of the twenty-fourth transistor is electrically connected to the first low-level power signal input terminal, a drain of the twenty-fourth transistor is electrically connected to the fifth node, a top gate of the twenty-fourth transistor is electrically connected to the sixth node, and a bottom gate of the twenty-fourth transistor is electrically connected to the potential control signal input terminal.

10 . The display device of claim 9 , wherein the reference signal sub-circuit further comprises:

a twenty-fifth transistor, wherein a top gate of the twenty-fifth transistor is electrically connected to the current-stage initialization signal input terminal, a source of the twenty-fifth transistor is electrically connected to a high-level power signal input terminal, and a drain of the twenty-fifth transistor is electrically connected to the fifth node;

a twenty-sixth transistor, wherein a source of the twenty-sixth transistor is electrically connected to a second high-level power signal input terminal, a top gate of the twenty-sixth transistor is electrically connected to the fifth node, and a drain of the twenty-sixth transistor is electrically connected to a reference signal output terminal;

a twenty-seventh transistor, wherein a top gate of the twenty-seventh transistor is electrically connected to the sixth node, a source of the twenty-seventh transistor is electrically connected to a second low-level power signal input terminal, and a drain of the twenty-seventh transistor is electrically connected to the reference signal output terminal;

a twenty-eighth transistor, wherein a drain of the twenty-eighth transistor is electrically connected to the sixth node, a source of the twenty-eighth transistor is electrically connected to the first low-level power signal input, and a top gate of the twenty-eighth transistor is electrically connected to the fifth node;

a twenty-ninth transistor, wherein a source of the twenty-ninth transistor is electrically connected to the high-level power signal input terminal, the drain of the twenty-ninth transistor is electrically connected to the sixth node, and the top gate of the twenty-ninth transistor is electrically connected to the seventh node;

a thirtieth transistor, wherein a top gate of the thirtieth transistor is electrically connected to the current-stage initialization signal input terminal, a source of the thirtieth transistor is electrically connected to the first low-level power signal input terminal, and a drain of the thirtieth transistor is electrically connected to the sixth node;

a third capacitor, wherein a first plate of the third capacitor is electrically connected to the fifth node, and a second plate of the third capacitor is electrically connected to the reference signal output terminal; and

a fourth capacitor, wherein a first plate of the fourth capacitor is electrically connected to the sixth node, and a second plate of the fourth capacitor is electrically connected to the seventh node.

11 . The display device according to claim 1 , wherein a voltage value of a signal input to the potential control signal input terminal is not greater than −5 volts.