Display panel
A display panel includes an amorphous silicon gate driver in which a lower voltage than the gate-off voltage output from the gate driver is applied to an adjacent stage as a low voltage transmission signal.
1 . A display device comprising:
a display area including a gate line; and
a gate driver electrically connected to the gate line, the gate driver including a plurality of stages and being integrated on a substrate,
wherein a stage of the plurality of stages comprises:
a first transistor including a control electrode electrically connected to a first node (Q), a first electrode electrically connected to a clock signal line, and a second electrode electrically connected to the gate line;
a sixth transistor including a control electrode electrically connected to a third transmission signal terminal from one of next stages, a first electrode electrically connected to a second low voltage terminal, and a second electrode electrically connected to the first node (Q);
a third transistor including a control electrode electrically connected to a second node (Q′) which is different from the first node, a first electrode electrically connected to a first low voltage terminal, and a second electrode electrically connected to the gate line; and
a seventeenth transistor including a first electrode electrically connected to the second low voltage terminal, and a second electrode electrically connected to a carry signal out terminal,
wherein the second low voltage is lower than the first low voltage.
2 . The display device of claim 1 , wherein the stage further comprises:
a fifth transistor including a control electrode electrically connected to a first transmission signal terminal from one of previous stages, and a second electrode electrically connected to the second node (Q′).
3 . The display device of claim 2 , wherein the stage further comprises:
an eleventh transistor including a control electrode electrically connected to the second node (Q′), a first electrode electrically connected to the second low voltage terminal, and a second electrode electrically connected to the carry signal out terminal.
4 . The display device of claim 3 , wherein the stage further comprises:
a fifteenth transistor including a control electrode electrically connected to the first node, a first electrode electrically connected to the clock signal line, and a second electrode electrically connected to the carry signal out terminal.
5 . The display device of claim 4 , wherein the stage further comprises:
a tenth transistor including a control electrode electrically connected to the second node, a first electrode electrically connected to the second low voltage terminal, and a second electrode electrically connected to the first node.
6 . The display device of claim 5 , wherein the stage further comprises:
a second transistor including a control electrode, a first electrode electrically connected to the first low voltage terminal, and a second electrode electrically connected to the gate line.
7 . The display device of claim 6 , wherein the stage further comprises:
a ninth transistor including a control electrode, a first electrode electrically connected to the second low voltage terminal via at least one transistor, and a second electrode electrically connected to the first node.