Semiconductor device and stack type semiconductor memory device including the same
A semiconductor memory device includes a core block including a plurality of unit memory blocks, a peripheral circuit block including a data input/output pad, a through electrode configured to exchange signals with another semiconductor memory device, and a data input/output circuit coupled to the through electrode, the core block, and the peripheral circuit block and configured to share one receiver in order to transmit a signal from the through electrode to the peripheral circuit block and in order to transmit a signal from the through electrode to the core block.
1 . A semiconductor memory device comprising:
a core block comprising a plurality of unit memory blocks;
a peripheral circuit block comprising a data input/output pad;
a through electrode configured to exchange signals with another semiconductor memory device; and
a data input/output circuit coupled to the through electrode, the core block, and the peripheral circuit block and configured to share one receiver in order to transmit a signal from the through electrode to the peripheral circuit block and in order to transmit a signal from the through electrode to the core block.
2 . The semiconductor memory device of claim 1 , wherein the peripheral circuit block comprises:
a deserializer configured to parallelize a signal that is output by the peripheral circuit block, and
a serializer configured to serialize a signal that is output by the core block.
3 . The semiconductor memory device of claim 1 , wherein the data input/output circuit comprises a read multiplexer configured to transmit, to the peripheral circuit block, a signal that is output by the one receiver in response to a multi-chip operation signal after a start of a read operation, and
an external processing signal line that is shared by the one receiver and the read multiplexer.
4 . The semiconductor memory device of claim 1 , wherein the data input/output circuit is configured to share one transmitter to transmit a signal from the core block to the through electrode and to transmit a signal from the peripheral circuit block to the through electrode.
5 . The semiconductor memory device of claim 4 , wherein the data input/output circuit is configured to transmit, to the one transmitter, a signal that is output by the peripheral circuit block in response to a multi-chip operation signal after a start of a write operation.
6 . A semiconductor memory device comprising:
a core block comprising a plurality of unit memory blocks;
a peripheral circuit block comprising a data input/output pad;
a through electrode configured to exchange signals with another semiconductor memory device;
a receiver coupled to the through electrode;
a read multiplexer configured to transmit, to the peripheral circuit block, an output signal that is output by the receiver in response to a multi-chip operation signal after a start of a read operation; and
an external processing signal line that is shared by the receiver and the read multiplexer.
7 . The semiconductor memory device of claim 6 , wherein the receiver is configured to be activated in response to a write signal, the multi-chip operation signal, a master chip distinction signal, and another chip pipe control signal and to output, to the external processing signal line, a signal that is transmitted through the through electrode.
8 . The semiconductor memory device of claim 6 , wherein the read multiplexer is configured to selectively output a plurality of signals to the peripheral circuit block or the external processing signal line in response to the multi-chip operation signal, the write signal, and a pipe control signal.
9 . The semiconductor memory device of claim 6 , further comprising:
a transmitter coupled to the through electrode, and
a write multiplexer configured to transmit, to the transmitter, a signal that is output by the peripheral circuit block in response to the multi-chip operation signal after a start of a write operation.
10 . The semiconductor memory device of claim 9 , wherein the external processing signal line is shared by the write multiplexer, the transmitter, the receiver, and the read multiplexer.
11 . The semiconductor memory device of claim 9 , wherein the transmitter is configured to be activated in response to a write signal, a master chip distinction signal, and a pipe control signal and to transmit, to the through electrode, a signal of the external processing signal line.
12 . The semiconductor memory device of claim 9 , wherein the write multiplexer is configured to selectively output a plurality of signals to the peripheral circuit block or the external processing signal line in response to the multi-chip operation signal, a write signal, and a master chip distinction signal.
13 . A stack type semiconductor memory device comprising:
a plurality of semiconductor chips that are coupled through a plurality of through electrodes,
wherein at least one of the plurality of semiconductor chips comprises a core block comprising a plurality of unit memory blocks, a peripheral circuit block comprising a data input/output pad, a through electrode configured to exchange signals with another semiconductor memory device, and a data input/output circuit,
wherein the data input/output circuit comprises,
an external processing signal line,
a read multiplexer configured to selectively output a plurality of signals to the peripheral circuit block or the external processing signal line,
a write multiplexer configured to selectively output a plurality of signals to the peripheral circuit block or the external processing signal line,
a receiver configured to transmit a signal from the through electrode to the peripheral circuit block and to transmit a signal from the through electrode to the core block, and
a transmitter configured to transmit a signal from the core block to the through electrode and to transmit a signal from the peripheral circuit block to the through electrode.
14 . The stack type semiconductor memory device of claim 13 , wherein the read multiplexer is configured to operate in response to a multi-chip operation signal and a pipe control signal after a start of a read operation.
15 . The stack type semiconductor memory device of claim 14 , wherein the write multiplexer is configured to operate in response to the multi-chip operation signal and a master chip distinction signal after a start of a write operation.
16 . The stack type semiconductor memory device of claim 13 , wherein the external processing signal line is shared by the write multiplexer, the transmitter, the receiver, and the read multiplexer.
17 . The stack type semiconductor memory device of claim 13 , wherein:
at least any one of the plurality of semiconductor chips is configured to operate as a master chip, and remaining semiconductor chips are configured to operate as slave chips, and
after a start of a write operation for the slave chip, the write multiplexer of the slave chip is configured to block an input from the peripheral circuit block.
18 . The stack type semiconductor memory device of claim 17 , wherein after a start of a read operation for the slave chip, the read multiplexer of the master chip is configured to block an input from the core block.