Memory circuit arrangement for accurate and secure read
The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.
1 . A device, comprising:
a primary memory array that includes:
a first configurable row having a first plurality of memory cells including a first plurality of test data cells and a first plurality of complementary test data cells in a first configuration and having a first data set; and
a second configurable row having a second plurality of memory cells including a second plurality of test data cells and a second plurality of complementary test data cells in the first configuration and having the first data set,
wherein the first and second configurable rows store the first data set in a first operation time period and, in a second operation time period, the first configurable row has a second data set in the first plurality of memory cells in a second configuration and the second configurable row has the second data set in the second plurality of memory cells in the second configuration.
2 . The device of claim 1 , wherein the primary memory array in operation averages corresponding data from the first plurality of test data cells from the first configurable row and the second plurality of test data cells from the second configurable row.
3 . The device of claim 1 , wherein the primary memory array includes a third configurable row having a third plurality of memory cells including a third plurality of test data cells and a third plurality of complementary test data cells in the first configuration and having the first data set and in operation, the primary memory array in operation averages corresponding data from the first plurality of test data cells from the first configurable row, the second plurality of test data cells from the second configurable row, and the third plurality of test data cells from the third configurable row.
4 . The device of claim 1 , wherein the first and second configurable rows store the first data set in the first operation time period and in the second operation time period the first configurable row has the second data set in the first plurality of memory cells and the second configurable row has a third data set in the second plurality of memory cells, the second and third data sets being different.
5 . A device, comprising:
a memory array, including:
a first configurable row having a first plurality of memory cells including a first plurality of test data cells and a first plurality of complementary test data cells, the first configurable row having a first data set; and
a second configurable row having a second plurality of memory cells including a second plurality of test data cells, the second configurable row having the first data set,
wherein the memory array averages data from the first plurality of test data cells from the first configurable row and the second plurality of test data cells from the second configurable row,
wherein the first and second configurable rows store the first data set in a first operation time period and, in a second operation time period, the first configurable row has a second data set in the first plurality of memory cells in a second configuration and the second configurable row has the second data set in the second plurality of memory cells in the second configuration.
6 . The device of claim 5 , wherein the memory array includes a third configurable row having a third plurality of memory cells including a third plurality of test data cells, the third configurable row having the first data set, the memory array averaging corresponding data from the first plurality of test data cells from the first configurable row, the second plurality of test data cells from the second configurable row, and the third plurality of test data cells from the third configurable row.
7 . The device of claim 5 , wherein the first and second configurable rows store the first data set in the first operation time period and in the second operation time period the first configurable row has the second data set in the first plurality of memory cells and the second configurable row has a third data set in the second plurality of memory cells, the second and third data sets being different.
8 . The device of claim 6 , wherein the second configurable row includes a second plurality of complementary test data cells and the third configurable row includes a third plurality of complementary test data cells.
9 . A device, comprising:
a memory array, including:
a first configurable memory row including a first test data cell and a first complementary test data cell, the first configurable memory row having a first data set; and
a second configurable memory row including a second test data cell and a second complementary test data cell, the second configurable memory row having the first data set,
wherein the first and second configurable memory rows store the first data set in a first operation time period and, in a second operation time period, the first configurable memory row has a second data set and the second configurable memory row has the second data set.
10 . The device of claim 9 , wherein the first configurable memory row and the second configurable memory row each include a plurality of differential read cells.
11 . The device of claim 9 , wherein the first configurable memory row and the second configurable memory row each include a plurality of single ended read cells.
12 . The device of claim 9 , wherein the first test data cell in the first configurable memory row is identical to the second test data cell in the second configurable memory row.
13 . The device of claim 12 , wherein a first configuration of cells of the first configurable memory row is identical to a second configuration of cells of the second configurable memory row, the first configuration of cells including the first test data cell and the first complementary test data cell and the second configuration of cells including the second test data cell and the second complementary test data cell.
14 . The device of claim 12 , wherein, to read the first and second configurable memory rows, a bitline coupled between the first and second configurable memory rows is discharged through the first test data cell and the second test data cell.
15 . The device of claim 14 , wherein the bitline carries a current that is an average of a first current of the first test data cell and a second current of the second test data cell.
16 . The device of claim 12 , wherein the first complementary test data cell in the first configurable memory row is identical to the second complementary test data cell in the second configurable memory row.
17 . The device of claim 16 , wherein, to complete a single ended read of the first and second configurable memory rows, a bitline coupled between the first and second configurable memory rows is discharged through the first complementary test data cell and the second complementary test data cell.
18 . The device of claim 9 , wherein the first configurable memory row is coupled to a first word line driver and the second configurable memory row is coupled to a second word line driver.