Memory device including pipe latch

1 . A pipeline system comprising:

a first inverter latch configured to receive plural data entries sequentially input;

plural second inverter latches coupled to each other in parallel for storing the plural data entries input from the first inverter latch in a distributive manner;

plural first switches arranged between the first inverter latch and each of the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches;

plural second switches configured to output the plural data entries stored in the plural second inverter latches; and

a tri-state inverter configured to control transmission of the plural data entries into the first inverter latch based on a clock signal.

2 . The pipeline system according to claim 1 , wherein each of the plural first switches comprises a pass gate operating in response to a pipe input signal and an inverted pipe input signal.

3 . The pipeline system according to claim 1 , wherein the plural first switches are controlled by plural pipe input signals which are sequentially activated based on the clock signal.

4 . The pipeline system according to claim 1 , wherein each of the plural second switches comprises a transistor operating in response to a pipe output signal.

5 . The pipeline system according to claim 1 , wherein the first inverter latch and the plural second inverter latches have a substantially same structure.

6 . The pipeline system according to claim 1 , wherein each of the second inverter latches comprises:

four transistors including each two transistors having gates cross-coupled to each other; and

a pull-down driver coupled to the four transistors.

7 . The pipeline system according to claim 6 , wherein the pull-down driver comprises an NMOS transistor.

8 . The pipeline system according to claim 6 , wherein the four transistors comprise two PMOS transistors and two NMOS transistors.

9 . A memory device comprising

a first input and output circuit configured to input or output plural data entries to or from a cell array comprising plural memory cells;

a pipe latch coupled to the first input and output circuit and configured to perform a parallel processing of the plural data entries based on a clock signal; and

a second input and output circuit coupled to the pipe latch and configured to input or output the plural data entries,

wherein the pipe latch comprises:

a first inverter latch configured to receive the plural data entries sequentially input;

plural second inverter latches coupled in parallel and configured to store the plural data entries input from the first inverter latch in a distributive manner and output the stored plural data entries; and

a tri-state inverter configured to control transmission of the plural data entries into the first inverter latch based on the clock signal.

10 . The memory device according to claim 9 , wherein the pipe latch comprises:

plural first switches arranged between the first inverter latch and the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches; and

plural second switches configured to output the plural data entries stored in the plural second inverter latches.

11 . The memory device according to claim 10 , wherein each of the plural first switches comprises a pass gate operating in response to a pipe input signal and an inverted pipe input signal.

12 . The memory device according to claim 10 , wherein the plural first switches are controlled by plural pipe input signals which are sequentially activated based on the clock signal.

13 . The memory device according to claim 10 , wherein each of the plural second switches comprises a transistor operating in response to a pipe output signal.

14 . The memory device according to claim 10 , wherein the first inverter latch and each of the plural second inverter latches have a substantially same structure.

15 . The memory device according to claim 10 , wherein each of the second inverter latches comprises:

four transistors including each two transistors having gates cross-coupled to each other; and

a pull-down driver coupled to the four transistors.

16 . The memory device according to claim 15 , wherein the pull-down driver comprises an NMOS transistor.

17 . The memory device according to claim 15 , wherein the four transistors comprise two PMOS transistors and two NMOS transistors.

18 . The memory device according to claim 9 , wherein the first input and output circuit comprises a sense amplifier, and the second input and output circuit comprises a chip select decoder.