IP Library Granted Patent US 12694921
Granted Patent B2
US 12694921 · App. 18/333,135 · Granted Jul 28, 2026

Dynamic memory operations

Inventors: Divya Madapusi Srinivas Prasad (Santa Clara, CA); Michael Ignatowski (Austin, TX)
Assignee: Advanced Micro Devices, Inc.
G11C11/40626G11C11/40615G11C11/40622
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Quick Facts
Patent No.
US 12694921
App. No.
18/333,135
Granted
Jul 28, 2026
Kind
B2
Abstract

Dynamic memory operations are described. In accordance with the described techniques, a system includes a stacked memory and one or more memory monitors configured to monitor conditions of the stacked memory. A system manager is configured to receive the monitored conditions of the stacked memory from the one or more memory monitors, and dynamically adjust operation of the stacked memory based on the monitored conditions. In one or more implementations, a system includes a memory and at least one register configured to store a ranking for each of a plurality of portions of the memory. Each respective ranking is determined based on an associated retention time of the respective portion of the memory. A memory controller is configured to dynamically refresh the portions of the memory at different times based on the ranking for each of the plurality of portions of the memory stored in the at least one register.

Claims (34)

1 . A system comprising:

a stacked dynamic random-access memory (DRAM) in a package;

a controller to interface with the stacked DRAM;

one or more memory monitors configured to detect conditions of the stacked DRAM; and

a system manager implemented on a processor chip in the package and configured to:

receive the detected conditions of the stacked DRAM from the one or more memory monitors; and

interface with one or more systems to dynamically adjust at least one of a voltage or a frequency for operating individual DRAM die of the stacked DRAM based on the detected conditions.

2 . The system of claim 1 , wherein the system manager dynamically adjusts operation of a logic die coupled to the stacked DRAM.

3 . The system of claim 1 , wherein the detected conditions include at least one of thermal conditions or voltage droop conditions of the stacked DRAM.

4 . The system of claim 1 , wherein the one or more memory monitors detect conditions of different portions of the stacked DRAM.

5 . The system of claim 1 , wherein the stacked DRAM includes a plurality of dies, and wherein the one or more memory monitors include a memory monitor for each of the plurality of dies of the stacked DRAM.

6 . The system of claim 1 , wherein the system manager is configured to adjust operation of a logic die coupled to the stacked DRAM by throttling the frequency or the voltage to prevent overheating of at least a portion of the logic die.

7 . The system of claim 1 , wherein the one or more systems include at least one of an adaptive voltage scaling system, an adaptive voltage frequency scaling system, or a dynamic voltage frequency system.

8 . The system of claim 1 , wherein the system manager is configured to adjust operation of the stacked DRAM by providing change signals to change the voltage or the frequency for operating one or more portions of the stacked DRAM.

9 . The system of claim 1 , wherein the system manager is configured to adjust operation of the stacked DRAM by refreshing one or more portions of the stacked DRAM.

10 . A device in a package communicably coupled to a stacked dynamic random-access memory (DRAM) in the package and one or more memory monitors, the device comprising:

a controller to interface with the stacked DRAM; and

a system manager implemented on a processor chip in the package configured to:

receive conditions of the stacked DRAM detected by the one or more memory monitors; and

interface with one or more systems to dynamically adjust at least one of a voltage or a frequency for operating individual DRAM die of the stacked DRAM based on the received conditions.

11 . The device of claim 10 , wherein the device is further configured to dynamically adjust operation of a logic die coupled to the stacked DRAM.

12 . The device of claim 10 , wherein the received conditions include at least one of thermal conditions or voltage droop conditions of the stacked DRAM.

13 . The device of claim 10 , wherein the received conditions are detected for different portions of the stacked DRAM.

14 . The device of claim 10 , wherein the device is further configured to adjust operation of a logic die coupled to the stacked DRAM by throttling the frequency or the voltage to prevent overheating of at least a portion of the logic die.

15 . The device of claim 10 , wherein the device is further configured to adjust operation of a logic die coupled to the stacked DRAM by providing change signals to change the voltage or frequency for operating one or more portions of the logic die.

16 . The device of claim 10 , wherein the device is further configured to adjust operation of the stacked DRAM by refreshing one or more portions of the stacked DRAM.

17 . The device of claim 16 , wherein the one or more portions of the stacked DRAM comprise different dies of the stacked DRAM.

18 . The device of claim 16 , wherein the one or more portions of the stacked DRAM correspond to individual rows of the stacked DRAM.

19 . The device of claim 16 , wherein the one or more portions of the stacked DRAM correspond to individual banks of the stacked DRAM.

20 . A method comprising:

detecting, by one or more memory monitors, conditions of a stacked dynamic random-access memory (DRAM) in a package;

interfacing, by a controller in the package, with the stacked DRAM;

receiving, by a system manager in the package, the detected conditions of the stacked DRAM from the one or more memory monitors; and

interfacing, by the system manager in the package, with one or more systems to dynamically adjust at least one of a voltage or a frequency for operating individual DRAM die of the stacked DRAM based on the detected conditions.