Data destruction via dram refresh suppression
A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.
1 . A dynamic random access memory (DRAM) device, comprising:
an interface to receive, from an external device, a first programming command that writes a first value corresponding to a first address of a first row of a plurality of rows of a memory array of the DRAM device into a first refresh address mask register that is to store the first value, the first value indicating that the first row is not to be refreshed where the first value is also received from the external device;
a first refresh address compare mask register to store a first address mask value, the first address mask value configurable to remove a variable number of bits from the first value stored by the first refresh address mask register from being used to determine whether the first row is to not be refreshed; and
circuitry to, based on the first value stored by the first refresh address mask register, prevent the first row from being refreshed.
2 . The DRAM device of claim 1 , wherein the interface is to further receive, from the external device, a second indicator of a second value associated with a second address of a second row of the plurality of rows of the memory array of the DRAM device that is to be refreshed, the DRAM device further comprising:
circuitry to, based on the second indicator, refresh the second row.
3 . The DRAM device of claim 1 , further comprising:
a plurality of refresh mask registers that include the first refresh address mask register to store a plurality of values corresponding to whether respective ones of the plurality of rows are to be refreshed.
4 . The DRAM device of claim 3 , further comprising:
a refresh count register to store a count value.
5 . The DRAM device of claim 4 , wherein when the count value stored by the refresh count register meets a threshold criteria, the first row is not prevented from being refreshed.
6 . The DRAM device of claim 5 , wherein each read operation of the first row adjusts the count value stored by the refresh count register.
7 . The DRAM device of claim 6 , wherein based on the count value stored by the refresh count register, a read of the first row is prevented.
8 . A dynamic random access memory (DRAM) device, comprising:
a memory array having a plurality of rows of memory cells that include a first row associated with a first row address value;
a plurality of refresh address mask registers, the plurality of refresh address mask registers including a first refresh address mask register, the first refresh address mask register to store the first row address value;
a plurality of refresh address compare mask registers, the plurality of refresh address compare mask registers including a first refresh address compare mask register to store a first address compare mask value;
an interface to receive, from an external device, at least one programming command that writes the first row address value into the first refresh address mask register and writes the first address compare mask value into the first refresh address compare mask register, where the first row address value and the first address compare mask value are also received from the external device; and
the DRAM device to, based on the first row address value stored in the first refresh address mask register and the first address compare mask value stored in the first refresh address compare mask register, not perform a first plurality of refresh operations on the first row.
9 . The DRAM device of claim 8 , wherein the interface is to further receive, from the external device, a second address indicator and the DRAM device is to, based on the second address indicator, perform refresh operations on a second row of the plurality of rows.
10 . The DRAM device of claim 8 , wherein the interface is to receive a first address compare mask value that prevents refresh operations on a second row.
11 . The DRAM device of claim 10 , further comprising:
a refresh count register to store a count value.
12 . The DRAM device of claim 11 , wherein the interface is to receive a count indicator that sets an initial count value stored by the refresh count register.
13 . The DRAM device of claim 8 , wherein when the count value stored by the refresh count register meets a first threshold criteria, the DRAM device allows the performance of a second plurality of refresh operations on the first row.
14 . The DRAM device of claim 13 , wherein each read operation of the first row adjusts the count value stored by the refresh count register.
15 . The DRAM device of claim 14 , wherein when the count value stored by the refresh count register meets a second threshold criteria, the DRAM device prevents the performance of read operations on the first row.
16 . A dynamic random access memory (DRAM) device, comprising:
a memory array having a plurality of rows of memory cells;
a plurality of refresh mask registers each associated with respective ones of the plurality of rows of memory cells, the plurality of refresh mask registers including a first refresh mask register associated with a first row of the plurality of rows of memory cells and a second refresh mask register associated with a second row of the plurality of rows of memory cells;
an interface configured to receive, from an external device, a first programming command that writes a first mask value into the first refresh mask register and a second programming command that writes a second mask value into the second refresh mask register, where the first mask value and the second mask value are also received from the external device; and
first circuitry to, based on the first mask value stored by the first refresh mask register, not perform refresh operations on the first row, and to, based on the second mask value stored by the second refresh mask register, perform refresh operations on the second row of the plurality of rows.
17 . The DRAM device of claim 16 ,
wherein the interface is to receive, from the external device, commands that include read commands and write commands directed to the second row.
18 . The DRAM device of claim 17 , wherein, based on a first read command received via the interface and from the external device, the second value stored by the second refresh mask register is changed to the first value.
19 . The DRAM device of claim 18 , wherein, based on a first write command received via the interface and from the external device, the second value is stored in the first refresh mask register.
20 . The DRAM device of claim 16 , wherein read commands decrement values stored by the first refresh mask register.