Low-power output driver for power-supply termination in memory interface applications
An output driver is disclosed that can include a delay generator configured to produce a plurality of delay signals in response to an input signal; a pre-driver configured to produce a plurality of control signals based on the plurality of shifted delay signals; and a main driver configured to couple to a channel with an asymmetric termination and provide an output signal at a node of the main driver based in response to the plurality of control signals, wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination. In some embodiments, an asymmetric switching sequence can be included. In some embodiments, a pull-up diode can be engaged. In some embodiments, the output driver is arranged to operate with core voltages and core transistors.
1 . An output driver, comprising:
a delay generator configured to produce a plurality of delay signals in response to an input signal;
a pre-driver configured to produce a plurality of control signals based on rising and falling edges of the plurality of delay signals; and
a main driver configured to couple to a channel with an asymmetric termination and provide an output signal at a node of the main driver based in response to the plurality of control signals,
wherein the main driver includes a plurality of slices, each slice having a pull-up transistor and a pull-down transistor coupled to the node, the pull-up transistor and pull-down transistor of the plurality of slices being driven by the plurality of control signals,
wherein the plurality of control signals provides for an asymmetric switching sequence in the plurality of slices to provide an asymmetric response in the main driver in response to the asymmetric termination.
2 . The output driver of claim 1 , wherein the output voltage is a symmetric signal with matching rising and falling edges based on the asymmetric response.
3 . The output driver of claim 1 , wherein a spacing between rising and falling edges of the plurality of delay signals is set by slew rate control signals input to the delay generator.
4 . The output driver of claim 1 , wherein the node of the main driver is the coupled connection between the pull-up transistor and pull-down transistor of each of the plurality is slices, and wherein the plurality of control signals includes a pull-up signal coupled to a gate of the pull-up transistor and a pull-down signal coupled to a gate of the pull-down transistor of each of the plurality of slices.
5 . The output driver of claim 4 , wherein the plurality of control signals from the pre-driver indicates the asymmetric switching sequence triggered on rising and falling edges of the plurality of delay signals.
6 . The output driver of claim 5 , wherein the asymmetric switching sequence includes a first sequence for switching the pull-up transistors and the pull-down transistors of the plurality of slices on rising edges of the plurality of delay signals and a second sequence for switching the pull-up transistors and the pull-down transistors of the plurality of slices on falling edges of the plurality of shifted delay signals, wherein the first sequence and the second sequence are different.
7 . The output driver of claim 6 , wherein the plurality of slices in the main driver includes N slices wherein the N and the switching sequence depend on the on resistance of the main driver in relation with the on resistance of the main driver and the value of a termination resistance of the asymmetric termination.
8 . The output driver of claim 6 , wherein the plurality of slices includes N slices, the plurality of delay signals includes delay signals d 0 , d 1 , d 2 , and d 3 , and wherein the switching sequence includes,
on a rising edge of delay signal d 0 , a number n0_on_R pull-up transistors of the plurality of slices are turned on and a number n0_off_R pull-down transistors of the plurality of slices are turned off,
on a rising edge of delay signal d 1 , a number n1_on_R of additional pull-up transistors of the plurality of slices are turned on and a number n1_off_R of additional pull-down transistors of the plurality of slices are turned off;
on a rising edge of delay signal d 2 , a number n2_on_R of additional pull-up transistors of the plurality of slices are turned on and a number n2_off_R of additional pull-down transistors of the plurality of slices are turned off;
on a rising edge of delay signal d 3 , a number n3_on_R of additional pull-up transistors of the plurality of slices are turned on and a number n3_off_R of additional pull-down transistors of the plurality of slices are turned off;
on a falling edge of delay signal d 0 , a number n0_on_F of pull-down transistors of the plurality of slices are turned on and a number n0_off_F of pull-up transistors of the plurality of slices are turned off;
on a falling edge of delay signal d 1 , a number n1_on_F of additional pull-down transistors of the plurality of slices are turned on and a number n1_off_F of additional pull-up transistors of the plurality of slices are turned off;
on a falling edge of delay signal d 2 , a number n2_on_F of additional pull-down transistors of the plurality of slices are turned on and a number n2_off_F of additional pull-up transistors of the plurality of slices are turned off;
on a falling edge of delay signal d 3 , a number n3_on_F of additional pull-down transistors of the plurality of slices are turned on and a number n3_off_F of additional pull-up transistors of the plurality of slices are turned off,
wherein the sum of the number n0_on_R, the number n1_on_R, the number n2 on_R, and the number n3 on_R is equal to N,
wherein the sum of the number n0_off_R, the number n1_off_R, the number n2_off_R, and the number n3_off_R is equal to N,
wherein the sum of the number n0_on_F, the number n1_on_F, the number n2 on_F, and the number n3_on_F is equal to N, and
wherein the sum of the number n0_off_F, the number n1_off_F, the number n2_off_F, and the number n3_off_F is equal to N, and
wherein the switching sequence on the rising edge of delay signals d 0 , d 1 , d 2 , and d 3 differs from the switching sequence on the falling edge of delay signals d 0 , d 1 , d 2 , and d 3 .
9 . An output driver, comprising:
a delay generator configured to produce a plurality of delay signals in response to an input signal;
a pre-driver configured to produce a plurality of control signals based on the plurality of delay signals; and
a main driver configured to couple to a channel with an asymmetric termination and provide an output signal at a node of the main driver based in response to the plurality of control signals,
a level shifter that receives the plurality of delay signals and provides shifted delay signals,
wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination,
wherein the main driver includes a plurality of slices, each of the plurality of slices including a pull-up transistor coupled in series with a pull-down transistor between system voltage and a ground, wherein the node of the main driver is the coupled connection between the pull-up transistor and pull-down transistor of each of the plurality is slices, and wherein the plurality of control signals includes a pull-up signal coupled to a gate of the pull-up transistor and a pull-down signal coupled to a gate of the pull-down transistor of each of the plurality of slices,
wherein the level shifter includes an upper level shifter and a lower level shifter, the upper level shifter configured to shift voltage levels of the plurality of delay signals within a voltage level VDDA and a lower voltage level VSSREG to generate upper delay signals, and the lower level shifter configured to shift voltage levels of the plurality of delay signals within a voltage level VDDREG and a lower voltage VSSA to generate lower delay signals;
wherein the pre-driver includes a plurality of upper-level pre-drivers operating between the voltages VDDA and VSSREG in response to the upper delay signals to provide pull-up signals for each pull-up transistor in the plurality of slices, and a plurality of lower-level pre-drivers operating between the voltages VDDREG and VSSA in response to the lower delay signals to provide pull-down signals for each pull-down transistor in the plurality of slices; and
wherein the series coupled pull-up transistor and pull-down transistor of each of the plurality of slices operates between VDD and VSSA.
10 . The output driver of claim 9 , wherein a first transistor is coupled between the pull-up transistor and the node in each of the plurality of slices and a second transistor is coupled between the node and the pull-down transistor in each of the plurality of slices, each of the first transistor and the second transistor are arranged to be on.
11 . The output driver of claim 9 , wherein VDDA=1.1V, VSSA=0V, VDDREG=0.875V, and VSSREG-0.225V, wherein voltages in each transistor of the pre-driver and the main driver do not exceed VDDREG, and wherein transistors are core transistors.
12 . The output driver of claim 9 , further including:
a diode pre-driver configured to provide a diode enable signal in response to a subset of the plurality of delay signals; and
a diode block coupled to the node of the main driver, the diode block configured to provide current to the node during a rising edge of the output signal.
13 . The output driver of claim 12 , wherein the diode pre-driver asserts the diode enable signal on a rising edge of a first delay signal of the plurality of delay signals and removes the diode enable signal on a rising edge of a second delay signal of the plurality of delay signals.
14 . The output driver of claim 13 , wherein the diode block includes a plurality of diode blocks and wherein the diode enable signal is provided to a subset of the plurality of diode blocks to counter effects of a termination resistance of the asymmetric termination.
15 . The output driver of claim 12 , further including a level shifter to provide shifted delay signals to the diode pre-driver.
16 . A method of driving an output signal in a channel with an asymmetric termination, comprising:
receiving an input signal;
generating, in a delay generator, a plurality of delay signals in response to the input signal;
producing, in a pre-driver, a plurality of control signals based on rising and falling edges of the plurality of delay signals; and
providing, in a main driver, an output signal at a node that can be coupled to the channel with the asymmetric termination in response to the plurality of control signals,
wherein the main driver includes a plurality of slices, each slice having a pull-up transistor and a pull-down transistor coupled to the node, the pull-up transistor and pull-down transistor of the plurality of slices being driven by the plurality of control signals,
wherein the plurality of control signals provides for an asymmetric switching sequence in the plurality of slices to provide an asymmetric response in the main driver in response to the asymmetric termination.
17 . The method of claim 16 , wherein providing the output voltage includes providing a symmetric signal with matching rising and falling edges based on the asymmetric response.
18 . The method of claim 16 , wherein generating a plurality of delay signals includes providing a spacing between rising and falling edges of the plurality of delay signals in accordance with slew rate control signals.
19 . The method of claim 16 , wherein the node of the main driver is the coupled connection between the pull-up transistor and pull-down transistor of each of the plurality is slices, and wherein the plurality of control signals includes a pull-up signal coupled to a gate of the pull-up transistor and a pull-down signal coupled to a gate of the pull-down transistor of each of the plurality of slices.
20 . The method of claim 19 , wherein the plurality of control signals from the pre-driver indicates the asymmetric switching sequence triggered on rising and falling edges of the plurality of delay signals, and wherein providing the output signal includes executing the switching sequence.
21 . The method of claim 20 , wherein the asymmetric switching sequence includes a first sequence for switching the pull-up transistors and the pull-down transistors of the plurality of slices on rising edges of the plurality of delay signals and a second sequence for switching the pull-up transistors and the pull-down transistors of the plurality of slices on falling edges of the plurality of shifted delay signals, wherein the first sequence and the second sequence are different.
22 . The method of claim 21 , wherein the plurality of slices in the main driver includes N slices wherein the N and the switching sequence depend on the on resistance of the main driver in relation with the on resistance of the main driver and the value of a termination resistance of the asymmetric termination.
23 . The method of claim 21 , wherein the plurality of slices includes N slices, the plurality of delay signals includes delay signals d 0 , d 1 , d 2 , and d 3 , and wherein the switching sequence includes,
on a rising edge of delay signal d 0 , a number n0_on_R of pull-up transistors of the plurality of slices are turned on and a number n0_off_R of pull-down transistors of the plurality of slices are turned off;
on a rising edge of delay signal d 1 , a number n1_on_R of additional pull-up transistors of the plurality of slices are turned on and a number n1_off_R of additional pull-down transistors of the plurality of slices are turned off;
on a rising edge of delay signal d 2 , a number n2_on_R of additional pull-up transistors of the plurality of slices are turned on and a number n2_off_R of additional pull-down transistors of the plurality of slices are turned off;
on a rising edge of delay signal d 3 , a number n3_on_R of additional pull-up transistors of the plurality of slices are turned on and a number n3_off_R of additional pull-down transistors of the plurality of slices are turned off;
on a falling edge of delay signal d 0 , a number n0_on_F of pull-down transistors of the plurality of slices are turned on and a number n0_off_F of pull-up transistors of the plurality of slices are turned off;
on a falling edge of delay signal d 1 , a number n1_on_F of additional pull-down transistors of the plurality of slices are turned on and a number n1_off_F of additional pull-up transistors of the plurality of slices are turned off,
on a falling edge of delay signal d 2 , a number n2_on_F of additional pull-down transistors of the plurality of slices are turned on and a number n2_off_F of additional pull-up transistors of the plurality of slices are turned off;
on a falling edge of delay signal d 3 , a number n3_on_F of additional pull-down transistors of the plurality of slices are turned on and a number n3_off_F of additional pull-up transistors of the plurality of slices are turned off,
wherein a sum of the number n0_on_R, the number n1_on_R, the number n2 on_R, and the number n3_on_R is equal to N,
wherein a sum of the number n0_off_R, the number n1_off_R, the number n2_off_R, and the number n3_off_R is equal to N,
wherein a sum of the number n0_on_F, the number n1_on_F, the number n2_on_F, and the number n3_on_F is equal to N, and
wherein a sum of the number n0_off_F, the number n1_off_F, the number n2_off_F, and the number n3_off_F is equal to N, and
wherein the switching sequence on the rising edge of delay signals d 0 , d 1 , d 2 , and d 3 differs from the switching sequence on the falling edge of delay signals d 0 , d 1 , d 2 , and d 3 .
24 . A method of driving an output signal in a channel with an asymmetric termination, comprising:
receiving an input signal;
generating, in a delay generator, a plurality of delay signals in response to the input signal;
producing, in a pre-driver, a plurality of control signals based on the plurality of delay signals; and
providing, in a main driver, an output signal at a node that can be coupled to the channel with the asymmetric termination in response to the plurality of control signals,
wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination,
wherein the main driver includes a plurality of slices, each of the plurality of slices including a pull-up transistor coupled in series with a pull-down transistor between system voltage and a ground,
wherein the node of the main driver is the coupled connection between the pull-up transistor and pull-down transistor of each of the plurality is slices, and wherein the plurality of control signals includes a pull-up signal coupled to a gate of the pull-up transistor and a pull-down signal coupled to a gate of the pull-down transistor of each of the plurality of slices;
level shifting, in an upper level shifter, the plurality of delay signals to be within a voltage level VDDA and a lower voltage level VSSREG to generate upper delay signals;
level shifting, in a lower level shifter, the plurality of delay signals to be within a voltage level VDDREG and a lower voltage VSSA to generate lower delay signals;
producing, in a plurality of upper-level pre-drivers operating between the voltages VDDA and VSSREG, pull-up signals in response to the upper delay signals for each pull-up transistor in the plurality of slices;
producing, in a plurality of lower-level pre-drivers operating between the voltages VDDREG and VSSA, pull-down signals in response to the lower delay signals for each pull-down transistor in the plurality of slices; and
wherein the series coupled pull-up transistor and pull-down transistor of each of the plurality of slices operates between VDD and VSSA.
25 . The method of claim 24 , further including protecting each of the plurality of pull-up transistors and the plurality of pull-down transistors with a first transistor coupled between the pull-up transistor and the node in each of the plurality of slices and a second transistor coupled between the node and the pull-down transistor in each of the plurality of slices, each of the first transistor and the second transistor being on.
26 . The method of claim 24 , wherein VDDA=1.1V, VSSA=0V, VDDREG-0.875V, and VSSREG-0.225V, and wherein voltages in each transistor of the pre-driver and the main driver do not exceed VDDREG.
27 . The method of claim 24 , further including:
providing, in a diode pre-driver, a diode enable signal in response to a subset of the plurality of delay signals; and
providing, in a diode block coupled to the node of the main driver, a current to the node during a rising edge of the output signal.
28 . The method of claim 27 , wherein providing the diode enable signal includes asserting the diode enable signal on a rising edge of a first delay signal of the plurality of shifted delay signals; and
removing the diode enable signal on a rising edge of a second delay signal of the plurality of delay signals.
29 . The method of claim 28 , wherein the diode block includes a plurality of diode blocks and wherein the diode enable signal is provided to a subset of the plurality of diode blocks to counter effects of a termination resistance of the asymmetric termination.
30 . The method of claim 27 , further including level shifting the plurality of delay signals provided to the diode pre-driver.
31 . An output driver, comprising:
a delay generator configured to produce a plurality of delay signals in response to an input signal;
a pre-driver configured to produce a plurality of control signals based on the plurality of delay signals;
a main driver configured to couple to a channel with an asymmetric termination and provide an output signal at a node of the main driver based in response to the plurality of control signals;
a diode pre-driver configured to provide a diode enable signal in response to a subset of the plurality of delay signals; and
a diode block coupled to the node of the main driver, the diode block configured to provide current to the node during a rising edge of the output signal,
wherein the plurality of control signals provides for an asymmetric response in the main driver in response to the asymmetric termination.
32 . The output driver of claim 31 , wherein the diode pre-driver asserts the diode enable signal on a rising edge of a first delay signal of the plurality of delay signals and removes the diode enable signal on a rising edge of a second delay signal of the plurality of delay signals.
33 . The output driver of claim 32 , wherein the diode block includes a plurality of diode blocks and wherein the diode enable signal is provided to a subset of the plurality of diode blocks to counter effects of a termination resistance of the asymmetric termination.
34 . The output driver of claim 31 , further including a level shifter to provide shifted delay signals to the diode pre-driver.
35 . The output driver of claim 1 , further including:
a diode pre-driver configured to provide a diode enable signal in response to a subset of the plurality of delay signals; and
a diode block coupled to the node of the main driver, the diode block configured to provide current to the node during a rising edge of the output signal.
36 . A method of driving an output signal in a channel with an asymmetric termination, comprising:
receiving an input signal;
generating, in a delay generator, a plurality of delay signals in response to the input signal;
producing, in a pre-driver, a plurality of control signals based on the plurality of delay signals; and
providing, in a main driver, an output signal at a node that can be coupled to the channel with the asymmetric termination in response to the plurality of control signals,
wherein the plurality of control signals provides for an asymmetric switching sequence in the plurality of slices to provide an asymmetric response in the main driver in response to the asymmetric termination;
providing, in a diode pre-driver, a diode enable signal in response to a subset of the plurality of delay signals; and
providing, in a diode block coupled to the node of the main driver, a current to the node during a rising edge of the output signal.
37 . The method of claim 36 , wherein providing the diode enable signal includes asserting the diode enable signal on a rising edge of a first delay signal of the plurality of shifted delay signals; and
removing the diode enable signal on a rising edge of a second delay signal of the plurality of delay signals.
38 . The method of claim 37 , wherein the diode block includes a plurality of diode blocks and wherein the diode enable signal is provided to a subset of the plurality of diode blocks to counter effects of a termination resistance of the asymmetric termination.
39 . The method of claim 37 , further including level shifting the plurality of delay signals provided to the diode pre-driver.
40 . The method of claim 16 , further including:
providing, in a diode pre-driver, a diode enable signal in response to a subset of the plurality of delay signals; and
providing, in a diode block coupled to the node of the main driver, a current to the node during a rising edge of the output signal.