Systems and methods for extending delay in self-timed memory

1 . A method comprising:

determining a self-timed path (STP) circuit of a memory, wherein the STP circuit comprises at least one or more first delay elements of a plurality of delay elements on a first dummy wordline (DWL) and a dummy bitline (DBL) corresponding to write logic circuitry of the STP circuit;

determining a logic delay of the STP circuit based at least on a delay associated with the write logic circuitry, wherein the logic delay corresponds to a pulse width;

providing a first resistor-capacitor (RC) delay based on the logic delay, wherein:

the first RC delay comprises a duration associated with one or more signals propagating through the first DWL and the DBL, and

the first RC delay corresponds to a first augmentation of the pulse width;

providing the STP circuit with an extended DWL;

providing a second RC delay, wherein:

the second RC delay comprises a duration associated with one of the one or more signals propagating through the extended DWL; and

the second RC delay corresponds to a second augmentation of the pulse width, and

performing a write operation on the memory based on a combination of the pulse width and the first and second augmentations of the pulse width.

2 . The method of claim 1 , wherein the STP circuit comprises:

at least one or more second delay elements of the plurality of delay elements corresponding to read logic circuitry of the STP circuit, and wherein:

each of the one or more first and second delay elements comprise a buffer.

3 . The method of claim 1 , wherein the logic delay is based on a combination of:

the delay associated with the write logic circuitry;

a delay associated with one or more fixed delays; and

a delay associated with the read logic circuitry.

4 . The method of claim 1 , wherein:

the STP circuit is extended by incorporating the extended DWL in the STP circuit;

the extended DWL is determined based on a size of a memory instance of the memory.

5 . The method of claim 1 , further comprising:

modifying, by a voltage-controlled driver, the pulse width based on an operating voltage of the memory.

6 . The method of claim 5 , wherein:

the voltage-controlled driver is activated when the operating voltage is above an operating voltage threshold, and

the voltage-controlled driver is configured to reduce the pulse width.

7 . The method of claim 5 , wherein the voltage-controlled driver comprises:

a transistor device configured to modify a pulse width of the RC delay.

8 . The method of claim 7 , wherein:

the transistor device is configured to be controlled through one or more voltage-controlled pins; and

the one or more voltage-controlled pins correspond to:

first pins enabled at a first voltage, and

second pins enabled at a second voltage.

9 . The method of claim 5 , wherein the controlled driver comprises a voltage sensor.

10 . A method comprising:

determining a self-timed path (STP) circuit based on a first resistor-capacitor (RC) delay and a logic delay, wherein the first RC delay comprises a delay associated with a first dummy wordline (DWL) and a dummy bitline (DBL); and

extending the STP circuit based on a second RC delay, wherein the second RC delay comprises a delay associated with an extended DWL.

11 . The method of claim 10 , wherein:

the first RC delay and the logic delay correspond to a signal propagating though the first DWL and the DBL; and

the logic delay comprises one or more delay elements; and

each of the one or more delay elements comprise a buffer.

12 . The method of claim 10 , wherein the logic delay is based on a combination of:

a delay associated with write logic circuitry on the DWL and DBL of the STP circuit;

a delay associated with read logic circuitry on the DWL and DBL of the STP circuit; and

a delay associated with one or more fixed delays on the DWL and DBL of the STP circuit.

13 . The method of claim 10 , wherein the STP circuit is extended by incorporating the extended DWL in the STP circuit.

14 . The method of claim 10 , further comprising:

modifying, by a voltage-controlled driver, a pulse width of the STP circuit based on an operating voltage of the memory.

15 . The method of claim 14 , wherein when the operating voltage is above an operating voltage threshold, the voltage-controlled driver is activated to reduce the pulse width.

16 . The method of claim 14 , wherein the voltage-controlled driver comprises:

a transistor device configured to modify a pulse width of at least one of the first and the second RC delay.

17 . The method of claim 16 , wherein:

the transistor device is configured to be controlled through one or more voltage-controlled pins; and

the one or more voltage-controlled pins correspond to:

first pins enabled at a first voltage, and

second pins enabled at a second voltage.

18 . The method of claim 14 , wherein the voltage-controlled driver comprises a voltage sensor.

19 . A method comprising:

providing a first delay to a self-timed path (STP) circuit configured to track at least one of a read or a write operation, wherein the first delay corresponds to a duration of a circuit operation on a first dummy wordline (DWL) and dummy bitline (DBL); and

providing a second delay to the STP circuit for the write operation, wherein the second delay corresponds to a duration of the circuit operation on an extended DWL.

20 . A method of claim 19 , further comprising:

tuning, by the STP, the read operation; and

tuning, by the STP, the write operation, wherein:

the read operation is configured to be tuned based at least on a first resistor-capacitor (RC) delay and a logic delay; and

the write operation is configured to be tuned based at least on the first RC delay, the logic delay, a fixed delay, and a second RC delay.