Multi-port SRAM structures with cell size optimization
A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.
1 . A memory array, comprising:
a first memory cell; and
a second memory cell abutting the first memory cell,
wherein each of the first and second memory cells include:
first and second active regions, wherein each of the first and second active regions extends lengthwise in a first direction;
first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction, wherein each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction, wherein the first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell; and
a fifth gate structure, wherein the fifth gate structure extends lengthwise in the second direction, and the fifth gate structure is configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell,
wherein the second memory cell shares the fifth gate structure with the first memory cell,
wherein the seventh transistor is a pass-gate (PG) transistor of the read-port, the fifth transistor is a pull-up (PU) transistor of the write-port, and the fifth and seventh transistors share the second active region.
2 . The memory cell of claim 1 , wherein the second active region is disposed on an n-well, and the seventh transistor is a p-type transistor.
3 . The memory cell of claim 1 , wherein:
the fourth gate structure is configured to engage the first active region in forming the sixth transistor, and
the sixth transistor is a PG transistor of the write-port.
4 . The memory cell of claim 3 , wherein the sixth transistor is an n-type transistor, and the seventh transistor is a p-type transistor.
5 . The memory cell of claim 3 , wherein the fifth gate structure is disposed on an extension line of the fourth gate structure.
6 . The memory cell of claim 1 , further comprising:
a first dielectric feature stacked between an end of the fourth gate structure and an end of the fifth gate structure, wherein the first dielectric feature extends lengthwise in the first direction.
7 . The memory cell of claim 6 , further comprising:
a second dielectric feature abutting an end of the first gate structure, wherein the second dielectric feature extends lengthwise in the second direction, and the second dielectric feature extends downwardly deeper than the first dielectric feature.
8 . The memory cell of claim 1 , wherein the read-port is a first read-port, the memory cell further comprising:
a sixth gate structure, wherein the sixth gate structure extends lengthwise in the second direction, and the sixth gate structure is configured to engage the second active region in forming an eighth transistor of a second read-port of the memory cell.
9 . The memory cell of claim 8 , wherein the second active region is disposed on an n-well, and each of the seventh and eighth transistors is a p-type transistor.
10 . The memory cell of claim 8 , wherein:
the first gate structure is configured to engage the first active region in forming the first transistor,
the first transistor is a PG transistor of the write-port, and
the eighth transistor is a PG transistor of the second read-port.
11 . A memory array, comprising:
a first static random-access memory (SRAM) cell having a write-port and a read-port; and
a second SRAM cell having a write-port and a read-port, the second SRAM cell abutting the first SRAM cell,
wherein, inside the first SRAM cell:
the write-port includes at least a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass-gate (PG) transistor, the read-port includes at least a PG transistor,
the PG transistor in the write-port is an n-type transistor,
the PG transistor in the read-port is a p-type transistor,
the PU transistor in the write-port and the PG transistor in the read-port include channel regions disposed on a first active region,
the PD transistor of the write-port and the PG transistor of the write-port include channel regions disposed on a second active region, and
the second active region extends parallel to the first active region,
wherein the PG transistor in the read-port has a gate structure extending across a boundary between the first and second SRAM cells.
12 . The semiconductor device of claim 11 , wherein the read-port of the first SRAM cell is a first read-port of the first SRAM cell, the first SRAM cell further comprising:
a second read-port, wherein the second read-port includes a PG transistor,
wherein the PG transistor in the second read-port is a p-type transistor.
13 . The semiconductor device of claim 12 , wherein the PG transistor in the second read-port includes a channel region disposed on the first active region.
14 . The semiconductor device of claim 11 , wherein, inside the first SRAM cell:
the PU transistor of the write-port and the PD transistor of the write-port share a first gate structure,
the PG transistor of the write-port includes a second gate structure,
and
the gate structure of the PG transistor of the read-port is disposed on an extension line of the second gate structure.
15 . The semiconductor device of claim 14 , further comprising:
a gate-cut feature disposed between the second gate structure and the gate structure of the PG transistor of the read-port and isolating the second gate structure from the gate structure of the PG transistor of the read-port.
16 . The semiconductor device of claim 11 , wherein, inside the first SRAM cell, the PU transistor and the PD transistor of the write-port are a first PU transistor and a first PD transistor of the write-port, respectively, wherein the write-port further includes a second PU transistor and a second PD transistor, the second PU transistor includes a channel region disposed on the first active region, and the second PD transistor includes a channel region disposed on the second active region.
17 . A memory array, comprising:
a first static random-access memory (SRAM) cell, wherein the first SRAM cell includes a write-port and a read-port, the read-port of the first SRAM cell includes a first pass-gate (PG) transistor of a first conductivity type, the write-port of the first SRAM cell includes a first pull-up (PU) transistor of the first conductive type, and the first PG transistor and the first PU transistor share a same active region; and
a second SRAM cell, wherein the second SRAM cell includes a write-port and a read-port, the read-port of the second SRAM cell includes a second PG transistor of the first conductivity type, the write-port of the second SRAM cell includes a second PU transistor of the first conductivity type, and the second PG transistor and the second PU transistor share a same active region,
wherein the write-port of the first SRAM cell includes a third PG transistor of a second conductivity type opposite to the first conductivity type, and the write-port of the second SRAM cell includes a fourth PG transistor of the second conductivity type,
wherein the first PG transistor and the second PG transistor share a first gate structure that extends across a boundary between the first SRAM cell and the second SRAM cell.
18 . The memory array of claim 17 , further comprising:
an isolation feature extending across the boundary between the first SRAM cell and the second SRAM cell,
wherein the isolation feature extends from an end of a gate structure of the third PG transistor to an end of a gate structure of the fourth PG transistor.
19 . The memory array of claim 17 , wherein the first PG transistor and the second PG transistor are p-type transistors disposed on an n-well, and the n-well extends through the boundary between the first SRAM cell and the second SRAM cell.
20 . The memory array of claim 17 , wherein:
the read-port of the first SRAM cell is a first read-port of the first SRAM cell,
the read-port of the second SRAM cell is a first read-port of the second SRAM cell,
the first SRAM cell includes a second read-port including a third PG transistor,
the second SRAM cell includes a second read-port including a fourth PG transistor, and
the third PG transistor and the fourth PG transistor share a second gate structure that extends across the boundary between the first SRAM cell and the second SRAM cell.