Dual tracking for fly bit line static random access memory (SRAM) architecture

1 . A memory circuit, comprising:

a first portion of a memory array comprising a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction;

a first tracking cell disposed next to the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction;

a second portion of the memory array comprising a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment both extending along the first lateral direction, wherein the third bit line segment is vertically disposed above the first bit line segment;

a second tracking cell disposed next to the second portion of the memory array along the second lateral direction;

a first tracking circuit configured to activate the first tracking cell, in response to at least one of the first nominal memory cells being selected, wherein the first tracking circuit comprises: a first AND gate; and a first tracking word line coupled to a gate terminal of the first tracking cell; and

a second tracking circuit configured to activate the second tracking cell, in response to at least one of the second nominal memory cells being selected, wherein the second tracking circuit comprises: a second AND gate; and a second tracking word line coupled to a gate terminal of the second tracking cell.

2 . The memory circuit of claim 1 , wherein

the first AND gate has a first input terminal configured to receive a clock signal, and a second input terminal configured to receive a first control signal asserted to a first logic state when the at least one first nominal memory cell is selected; and

the second AND gate has a first input terminal configured to receive the clock signal, and a second input terminal configured to receive a second control signal asserted to the first logic state when the at least one second nominal memory cell is selected.

3 . The memory circuit of claim 2 , wherein the first AND gate is configured to assert the first tracking word line to the first logic state when the at least one first nominal memory cell is selected, and the second AND gate is configured to assert the second tracking word line to the first logic state when the at least one second nominal memory cell is selected.

4 . The memory circuit of claim 2 , wherein

the first tracking circuit further comprises:

a first NAND gate; and

a first inverter coupled to a first word line coupled to the at least one first nominal memory cell; and

the second tracking circuit comprises:

a second NAND gate; and

a second inverter coupled to a second word line coupled to the at least one second nominal memory cell.

5 . The memory circuit of claim 4 , wherein

the first NAND gate has a first input terminal configured to receive a first address signal asserted to the first logic state when the at least one first nominal memory cell is selected, and a second input terminal configured to receive a first signal present on a first tracking bit line coupled to the first tracking cell; and

the second NAND gate has a first input terminal configured to receive a second address signal asserted to the first logic state when the at least one second nominal memory cell is selected, and a second input terminal configured to receive a second signal present on a second tracking bit line coupled to the second tracking cell.

6 . The memory circuit of claim 4 , wherein a first signal present on the first word line has a first pulse width when the at least one first nominal memory cell is selected, and a second signal present on the second word line has a second pulse width when the at least one second nominal memory cell is selected.

7 . The memory circuit of claim 6 , wherein the first pulse width is narrower than the second pulse width.

8 . The memory circuit of claim 1 , wherein the first and second bit line segments are disposed in a first metallization layer, and the third bit line segment is disposed in a second metallization layer above the first metallization layer.

9 . A memory circuit, comprising:

a first portion of a memory array comprising a plurality of a first nominal memory cells;

a first bit line coupled to the first nominal memory cells, wherein the first bit line comprises a first bit line segment disposed in a first metallization layer;

a second portion of the memory array comprising a plurality of second nominal memory cells;

a second bit line coupled to the second nominal memory cells, wherein the second bit line comprises a second bit line segment and a third bit line segment disposed in the first metallization layer and a second metallization layer, respectively;

a first tracking cell configured to mimic each of the plurality of first nominal memory cells;

a second tracking cell configured to mimic each of the plurality of second nominal memory cells;

a first tracking circuit configured to activate the first tracking cell, in response to at least one of the first nominal memory cells being selected, wherein the first tracking circuit comprises:

a first AND gate; and a first tracking word line coupled to a gate terminal of the first tracking cell; and

a second tracking circuit configured to activate the second tracking cell, in response to at least one of the second nominal memory cells being selected, wherein the second tracking circuit comprises: a second AND gate; and a second tracking word line coupled to a gate terminal of the second tracking cell.

10 . The memory circuit of claim 9 , wherein

the first AND gate has a first input terminal configured to receive a clock signal, and a second input terminal configured to receive a first control signal asserted to a first logic state when the at least one first nominal memory cell is selected; and

the second AND gate has a first input terminal configured to receive the clock signal, and a second input terminal configured to receive a second control signal asserted to the first logic state when the at least one second nominal memory cell is selected.

11 . The memory circuit of claim 10 , wherein the first AND gate is configured to assert the first tracking word line to the first logic state when the at least one first nominal memory cell is selected, and the second AND gate is configured to assert the second tracking word line to the first logic state when the at least one second nominal memory cell is selected.

12 . The memory circuit of claim 10 , wherein

the first tracking circuit further comprises:

a first NAND gate; and

a first inverter coupled to a first word line coupled to the at least one first nominal memory cell; and

the second tracking circuit comprises:

a second NAND gate; and

a second inverter coupled to a second word line coupled to the at least one second nominal memory cell.

13 . The memory circuit of claim 12 , wherein a first signal present on the first word line has a first pulse width when the at least one first nominal memory cell is selected, and a second signal present on the second word line has a second pulse width when the at least one second nominal memory cell is selected.

14 . The memory circuit of claim 13 , wherein the first pulse width is narrower than the second pulse width.

15 . The memory circuit of claim 12 , wherein the first NAND gate has a first input terminal configured to receive a first address signal asserted to the first logic state when the at least one first nominal memory cell is selected, and a second input terminal configured to receive a first signal present on a first tracking bit line coupled to the first tracking cell.

16 . The memory circuit of claim 12 , wherein the second NAND gate has a first input terminal configured to receive a second address signal asserted to the first logic state when the at least one second nominal memory cell is selected, and a second input terminal configured to receive a second signal present on a second tracking bit line coupled to the second tracking cell.

17 . The memory circuit of claim 9 , wherein the third bit line segment is vertically disposed above the first bit line segment.

18 . A method for operating a memory circuit, comprising:

determining a selection of at least one nominal memory cell of a memory array, wherein the memory array comprises a first portion and a second portion, wherein the first portion comprises a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction, and the second portion comprises a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment both extending along the first lateral direction, wherein the third bit line segment is vertically disposed above the first bit line segment;

activating a first tracking cell by a first tracking circuit, in response to at least one of the first nominal memory cells being selected, wherein the first tracking cell is disposed next to the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction, wherein the first tracking circuit comprises: a first AND gate, wherein the first AND gate has a first input terminal configured to receive a clock signal; and a first tracking word line coupled to a gate terminal of the first tracking cell; and

activating a second tracking cell by a second tracking circuit, in response to at least one of the second nominal memory cells being selected, wherein the second tracking cell is disposed next to the second portion of the memory array along the second lateral direction, wherein the second tracking circuit comprises: a second AND gate, wherein the second AND gate has a first input terminal configured to receive the clock signal; and a second tracking word line coupled to a gate terminal of the second tracking cell.

19 . The method of claim 18 , comprising:

receiving a first control signal asserted to a first logic state when the at least one first nominal memory cell is selected; and

receiving a second control signal asserted to the first logic state when the at least one second nominal memory cell is selected.

20 . The method of claim 18 , wherein

the first tracking circuit further comprises:

a first NAND gate; and

a first inverter coupled to a first word line coupled to the at least one first nominal memory cell; and

the second tracking circuit comprises:

a second NAND gate; and

a second inverter coupled to a second word line coupled to the at least one second nominal memory cell.