Memory cell noise protection via bidirectional threshold switching devices
A memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter. An additional memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device between the first access transistor and the first node.
1 . A memory device comprising:
a first inverter;
a second inverter, wherein the first inverter and the second inverter are cross-coupled in a feedback loop;
a first access transistor for a first node of the feedback loop;
a second access transistor for a second node of the feedback loop, wherein the first node and the second node are to store complementary binary data bit values; and
a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter.
2 . The memory device of claim 1 , wherein the first inverter comprises: a first pull-up transistor and a first pull-down transistor, and wherein the second inverter comprises: a second pull-up transistor and a second pull-down transistor.
3 . The memory device of claim 1 , further comprising:
a wordline, wherein a first gate of the first access transistor and a second gate of the second access transistor are controlled via the wordline.
4 . The memory device of claim 1 , further comprising:
a first bitline; and
a second bitline, wherein the first access transistor is coupled to the first bitline and the first node of the feedback loop, and wherein the second access transistor is coupled to the second bitline and the second node of the feedback loop.
5 . The memory device of claim 4 , wherein for a write operation, the second bitline conveys an inverse signal from the first bitline.
6 . The memory device of claim 4 , further comprising:
a sense amplifier coupled to the first bitline and to the second bitline, wherein the sense amplifier is for a read operation.
7 . The memory device of claim 1 , wherein the bidirectional threshold switching device comprises a silver and oxide-based structure.
8 . The memory device of claim 1 , wherein the bidirectional threshold switching device comprises a metal and hafnium oxide-based structure.
9 . The memory device of claim 1 , wherein the bidirectional threshold switching device is configured with a positive threshold voltage to turn on, a positive hold voltage to turn off, a negative threshold voltage to turn on, and a negative hold voltage to turn off.
10 . The memory device of claim 9 , wherein the positive threshold voltage and the negative threshold voltage are symmetric, and where the positive hold voltage and the negative hold voltage are symmetric.
11 . The memory device of claim 9 , wherein the positive threshold voltage is greater than a transistor threshold voltage of a first pull-down transistor of the first inverter.
12 . The memory device of claim 1 , wherein the memory device comprises a static random access memory cell.
13 . The memory device of claim 1 , wherein the memory device comprises a multi-port static random access memory cell.
14 . The memory device of claim 1 , further comprising:
a second bidirectional threshold switching device in the feedback loop between an output of the first inverter and an input of the second inverter.
15 . A method comprising:
charging a first bitline and a second bitline of a memory cell to logic high values, the memory cell comprising:
a first inverter;
a second inverter, wherein the first inverter and the second inverter are cross-coupled in a feedback loop;
a first access transistor for a first node of the feedback loop;
a second access transistor for a second node of the feedback loop, wherein the first node and the second node are to store complementary binary data bit values, wherein the first access transistor is coupled to the first bitline and the first node of the feedback loop, and wherein the second access transistor is coupled to the second bitline and the second node of the feedback loop; and
a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter; and
activating a wordline of the memory cell, to open the first access transistor and the second access transistor;
preventing a voltage change for the first node via the bidirectional threshold switching device, in response to the activating of the wordline; and
generating an output value of the memory cell in response the activating of the wordline.
16 . A memory device comprising:
a first inverter;
a second inverter, wherein the first inverter and the second inverter are cross-coupled in a feedback loop;
a first access transistor for a first node of the feedback loop;
a second access transistor for a second node of the feedback loop, wherein the first node and the second node are to store complementary binary data bit values;
a wordline, wherein a first gate of the first access transistor and a second gate of the second access transistor are controlled by the wordline; and
a first bidirectional threshold switching device between the first access transistor and the first node.
17 . The memory device of claim 16 , further comprising:
a second bidirectional threshold switching device between the second access transistor and the second node.
18 . The memory device of claim 16 , wherein the first access transistor comprises a first read port access transistor, wherein the second access transistor comprises a second read port access transistor, wherein the wordline comprises a first wordline, and wherein the memory device further comprises:
a first bitline;
a second bitline, wherein the first read port access transistor is coupled to the first bitline, and wherein the second read port access transistor is coupled to the second bitline;
a first write port access transistor for the first node of the feedback loop;
a second write port access transistor for the second node of the feedback loop; and
a second wordline, wherein a first gate of the first write port access transistor and a second gate of the second write port access transistor are controlled by the second wordline.
19 . The memory device of claim 16 , wherein the first bidirectional threshold switching device is configured with a positive threshold voltage to turn on, a positive hold voltage to turn off, a negative threshold voltage to turn on, and a negative hold voltage to turn off.