Memory structure including high density three-dimensional NOR memory strings of junctionless ferroelectric storage transistors and method of fabrication
A memory structure including three-dimensional NOR memory strings and method of fabrication is disclosed. In some embodiments, a memory structure includes randomly accessible ferroelectric storage transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film storage transistors. The ferroelectric storage transistors are junctionless field-effect transistors having a ferroelectric polarization layer formed adjacent a semiconductor oxide layer as the channel region. The three-dimensional memory stacks are manufactured in a process that uses a sacrificial layer and access shafts to perform channel separation through a backside selective etch process.
1 . A three-dimensional memory structure formed above a planar surface of a semiconductor substrate, the memory structure comprising:
a plurality of thin-film ferroelectric storage transistors being organized as a plurality of stacks of NOR memory strings, the storage transistors within each NOR memory string sharing a common source layer and a common drain layer, spaced apart by a first isolation layer, with each layer extending along a first direction, the common source layer and the common drain layer comprising respectively a first conductive layer and a second conductive layer with the first isolation layer formed therebetween; wherein:
(i) each NOR memory string extends along the first direction that is substantially parallel to the planar surface of the semiconductor substrate;
(ii) the NOR memory strings of each stack are (a) provided one on top of another along a second direction substantially normal to the planar surface, and (b) isolated one from the other memory string by a second isolation layer;
(iii) a semiconductor oxide layer formed on the sidewalls of each stack of NOR memory strings and, with respect to each NOR memory string within the stack, in contact with the common source layer and the common drain layer of the NOR memory string along the sidewall of each stack, thus providing channel regions for the storage transistors of the NOR memory string;
(iv) a ferroelectric gate dielectric layer is provided adjacent the semiconductor oxide layer, the semiconductor oxide layer being provided between the ferroelectric gate dielectric layer and the first conductive layer of the common source layer, and further being provided between the ferroelectric gate dielectric layer and the second conductive layer of the common drain layer; and
(v) a plurality of conductors are provided between adjacent stacks of NOR memory strings, each conductor extending along the second direction, and each serving as a common gate electrode for a group of storage transistors in the NOR memory strings of the adjacent stacks,
wherein, within a stack of NOR memory strings, the semiconductor oxide layer for the storage transistors of a first NOR memory string are separated from the semiconductor oxide layer for the storage transistors of a second adjacent NOR memory string in the same stack in the second direction.
2 . The three-dimensional memory structure of claim 1 , wherein, within the stack of NOR memory strings, the semiconductor oxide layer for the storage transistors of a first NOR memory string are separated from the semiconductor oxide layer for the storage transistors of a second adjacent NOR memory string in the same stack in the second direction by the second isolation layer.
3 . The three-dimensional memory structure of claim 2 , wherein the second isolation layer comprises an air gap cavity.
4 . The three-dimensional memory structure of claim 3 , wherein the second isolation layer comprises a liner layer formed on exposed surfaces between memory strings within a stack of NOR memory strings and an air gap in the remaining cavity.
5 . The three-dimensional memory structure of claim 1 , wherein the storage transistors within each NOR memory string share the first conductive layer, which serves as a common drain line and share the second conductive layer, which serves as a common source line, the semiconductor oxide layer in contact with and in between the first and second conductive layers serving as a junctionless channel region of each storage transistor in each NOR memory string.
6 . The three-dimensional memory structure of claim 5 , wherein the common source line is an electrically floating source.
7 . The three-dimensional memory structure of claim 1 , wherein the semiconductor oxide layer comprises one of an indium gallium zinc oxide (IGZO) layer, an indium zinc oxide (IZO) layer, an indium tungsten oxide (IWO) layer, or an indium tin oxide (ITO) layer.
8 . The three-dimensional memory structure of claim 7 , wherein the semiconductor oxide layer comprises a first semiconductor oxide layer and a second semiconductor oxide layer, the first semiconductor oxide layer being provided in contact with the first and second conductive layers and providing a contact resistance to the first and second conductive layers lower than the contact resistance of the second semiconductor oxide layer.
9 . The three-dimensional memory structure of claim 1 , wherein the ferroelectric gate dielectric layer comprises a doped hafnium oxide layer.
10 . The three-dimensional memory structure of claim 1 , further comprising an interfacial dielectric layer formed between the semiconductor oxide layer and the ferroelectric gate dielectric layer.
11 . The three-dimensional memory structure of claim 10 , wherein the ferroelectric gate dielectric layer comprises a doped hafnium oxide layer and the interfacial dielectric layer comprises a high dielectric constant dielectric layer.
12 . The three-dimensional memory structure of claim 1 , wherein the conductive layer of each of the common source layer and the common drain layer comprises a metal layer.
13 . The three-dimensional memory structure of claim 1 , wherein the first isolation layer comprises a silicon oxide layer.
14 . The three-dimensional memory structure of claim 1 , further comprising a plurality of non-memory transistors formed in each NOR memory string, the non-memory transistors being designated as precharge transistors, the precharge transistors being activated during a precharge operation to electrically connect the common source layer and the common drain layer in each NOR memory string to set the voltage on the common source layer to equal to the voltage on the common drain layer.
15 . The three-dimensional memory structure of claim 1 , wherein the plurality of conductors forming the gate electrodes are provided in trenches formed between adjacent stacks of NOR memory strings, each conductor being spaced apart from an adjacent conductor by a dielectric filled shaft extending in the second direction.
16 . The three-dimensional memory structure of claim 1 , wherein the plurality of conductors in a first trench are formed offset in the first direction from the plurality of conductors in a second trench adjacent the first trench.
17 . The three-dimensional memory structure of claim 1 , wherein in each storage transistor in the NOR memory string, the common drain line and the common source line are biased to substantially the same voltage during a program or an erase operation of the storage transistor.
18 . The three-dimensional memory structure of claim 1 , wherein the first isolation layer comprises a first dielectric layer having a first dielectric constant formed adjacent the first conductive layer and a second dielectric layer having a second dielectric constant formed adjacent the second conductive layer, the first dielectric constant being larger than the second dielectric constant.
19 . The three-dimensional memory structure of claim 1 , wherein the first isolation layer comprises a first dielectric layer having a first dielectric constant formed adjacent the first conductive layer, a second dielectric layer having a second dielectric constant formed adjacent the second conductive layer, and a third dielectric layer having a third dielectric constant formed between the first and second dielectric layers, the first and second dielectric constants being larger than the third dielectric constant.
20 . The three-dimensional memory structure of claim 1 , wherein the first isolation layer comprises a dielectric layer having a dielectric constant greater than a dielectric constant of silicon oxide.