Memory device configured to apply different voltages to wirings depending on a current flowing through corresponding memory strings
A memory device includes first and second strings including transistors, a first wiring connected to the first string, a second wiring connected to the second string, a third wiring connected to both strings, and a circuit for executing a write operation on a first transistor of the first string and a second transistor of the second string. The operation includes a first operation by which a first voltage is applied to the wirings and a second operation by which a second voltage is applied to gates of the first and second transistors. When a current flows between the first and third wirings but does not flow between the second and third wirings in the first operation, the circuit causes a third voltage to be applied to the first wiring, and causes a fourth voltage higher than the third voltage to be applied to the second wiring in the second operation.
1 . A method performed by a memory device that includes:
a first memory string including a plurality of memory cell transistors that are connected in series,
a second memory string including a plurality of memory cell transistors that are connected in series,
a first wiring connected to one end of the first memory string,
a second wiring connected to one end of the second memory string, and
a third wiring connected to the other end of the first memory string and the other end of the second memory string, the method comprising:
executing a write operation on a first memory cell transistor, which is one of the memory cell transistors of the first memory string, and a second memory cell transistor, which is one of the memory cell transistors of the second memory string, the write operation including:
a first operation by which a first voltage is applied to the first and second wirings, and
a second operation by which a second voltage is applied to gates of the first and second memory cell transistors, wherein
the second operation includes:
upon detection of a current flowing between each of the first and second wirings and the third wiring in the first operation, applying a third voltage to the first and second wirings, and
upon detection of a current flowing between the first and third wirings in the absence of a current between the second and third wirings in the first operation, applying the third voltage to the first wiring, and applying a fourth voltage higher than the third voltage and lower than the second voltage to the second wiring.
2 . The method according to claim 1 , wherein, upon detection of a current flowing between the first and third wirings in the absence of a current between the second and third wirings in the first operation, data is written into the first memory cell transistor but is not written into the second memory cell transistor by the second operation.
3 . The method according to claim 1 , wherein the second voltage has a magnitude for increasing threshold voltages of the first and second memory cell transistors.
4 . The method according to claim 1 , wherein the third voltage is a ground voltage.
5 . The method according to claim 1 , wherein
the first operation includes applying a fifth voltage lower than the second voltage to gates of the memory cell transistors of the first and second memory strings, and applying the third voltage to the third wiring,
the fifth voltage has a magnitude for turning on the memory cell transistors of the first and second memory strings, and
the first voltage is higher than the third voltage.
6 . The method according to claim 1 , wherein
the first memory string includes a first transistor at said one end of the first memory string and a second transistor at the other end of the first memory string,
the second memory string includes a third transistor at said one end of the second memory string and a fourth transistor at the other end of the second memory string, and
the second operation includes applying a sixth voltage to gates of the first and third transistors, and applying the third voltage to gates of the second and fourth transistors.
7 . The method according to claim 6 , wherein
the first operation includes:
applying a fifth voltage lower than the second voltage to gates of the memory cell transistors of the first and second memory strings,
applying a seventh voltage to the gates of the first, second, third, and fourth transistors, and
applying the third voltage to the third wiring,
the fifth voltage has a magnitude for turning on the memory cell transistors of the first and second memory strings,
the first voltage is higher than the third voltage, and
the seventh voltage has a magnitude for turning on the first, second, third, and fourth transistors.
8 . The method according to claim 1 , wherein
the memory device includes a first latch circuit connected to the first wiring and a second latch circuit connected to the second wiring, and
the method further comprises:
storing first and second information indicating a result of the first operation in the first and second latch circuits, respectively.
9 . The method according to claim 8 , wherein storing first and second information includes: upon detection of a current flowing between the first and third wirings in the absence of a current between the second and third wirings in the first operation, storing, as the first information, a first value in the first latch circuit, and storing, as the second information, a second value different from the first value in the second latch circuit.