Semiconductor memory

1 . A semiconductor memory comprising:

a first memory cell configured to have one of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, an m-th threshold voltage higher than the second threshold voltage, or an n-th threshold voltage higher than the m-th threshold voltage, wherein m is a natural number, and n is a natural number equal to or greater than m;

a second memory cell configured to have one of the first to m-th threshold voltages;

a first word line coupled to the first and second memory cells;

a first bit line connected to the first memory cell;

a second bit line connected to the second memory cell;

a first sense amplifier connected to the first bit line;

a second sense amplifier connected to the second bit line;

a first switch provided between the first sense amplifier and the second sense amplifier; and

a controller,

wherein:

data of a first bit, a second bit, an i-th bit, and a j-th bit are stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell, wherein i is a natural number, j is a natural number equal to or greater than i, and n×n>2{circumflex over ( )}j, and

the controller is configured to:

in a first read operation for a first page that includes the first bit:

read first data of the first page from the first memory cell by applying at least one type of read voltage to the first word line;

read second data of the first page from the second memory cell by applying the at least one type of read voltage to the first word line; and

determine data of the first page based on the first data and the second data,

in a second read operation for a second page that includes the second bit:

read data of the second page from the second memory cell by applying at least two types of read voltage to the first word line, and

in a third read operation for a third page that includes a third bit:

read data of the third page from the first memory cell by applying at least two types of read voltage to the first word line.

2 . The semiconductor memory of claim 1 , wherein the at least one type of read voltage applied to the first word line during the first read operation is different from each of the at least two types of read voltage applied to the first word line during the second read operation.

3 . The semiconductor memory of claim 1 , wherein the at least two types of read voltage applied to the first word line during the second read operation are the same as the at least two types of read voltage applied to the first word line during the third read operation, respectively.

4 . The semiconductor memory of claim 1 , wherein the controller is configured to:

in a fourth read operation for a fourth page that includes a fourth bit:

read first data of the fourth page from the first memory cell by applying at least two types of read voltage to the first word line;

read second data of the fourth page from the second memory cell by applying the at least one type of read voltage to the first word line; and

determine data of the fourth page based on the first data and the second data, and

in a fifth read operation for a fifth page that includes a fifth bit:

read first data of the fifth page from the first memory cell by applying at least one type of read voltage to the first word line;

read second data of the fifth page from the second memory cell by applying the at least two types of read voltage to the second word line; and

determine data of the fifth page based on the first data and the second data.

5 . The semiconductor memory of claim 4 , wherein the at least one type of read voltage applied to the first word line during the fourth read operation is different from each of the at least two types of read voltage applied to the first word line during the fourth read operation.

6 . The semiconductor memory of claim 4 , wherein:

the at least one type of read voltage applied to the first word line during the fourth read operation is the same as the at least one type of read voltage applied to the first word line during the fifth read operation, and

the at least two types of read voltage applied to the first word line during the fourth read operation are the same as the at least two types of read voltage applied to the first word line during the fifth read operation, respectively.

7 . The semiconductor memory of claim 4 , wherein the at least one type of read voltage applied to the first word line during the first read operation is the same as (i) the at least one type of read voltage applied to the first word line during the fourth read operation and (ii) the at least one type of read voltage applied to the first word line during the fifth read operation.

8 . The semiconductor memory of claim 1 , wherein, in the first read operation, the data of the first page is determined through a logical operation between the first data stored in the first sense amplifier and the second data stored in the second sense amplifier by turning on the first switch.

9 . The semiconductor memory of claim 8 , wherein the first switch is turned off in each of the second read operation and the third read operation.

10 . The semiconductor memory of claim 1 , further comprising:

a third memory cell configured to have one of the first to m-th threshold voltages, the third memory cell being coupled to the first word line;

a fourth memory cell configured to have one of the first to m-th threshold voltages, the fourth memory cell being coupled to the first word line;

a third bit line connected the third memory cell;

a fourth bit line connected to the fourth memory cell;

a third sense amplifier connected to the third bit line;

a fourth sense amplifier connected to the fourth bit line; and

a second switch provided between the third sense amplifier and the fourth sense amplifier.

11 . The semiconductor memory of claim 10 , wherein no switch is provided between the second sense amplifier and the third sense amplifier.