Memory device

1 . A memory device comprising:

a mode register configured to store a first code for indicating termination resistance of the memory device and a second code for disabling a defective resistor; and

an output driver comprising a plurality of pull-up units including a plurality of pull-up resistors and a plurality of pull-down units including a plurality of pull-down resistors, wherein respective pull-up resistors and respective pull-down resistors are configured to be disabled or enabled based on the second code,

wherein the output driver is configured to enable, based on the first code, a subset of pull-up units from among the plurality of pull-up units including the respective enabled pull-up resistors based on the second code, and is configured to enable, based on the first code, a subset of pull-down units from among the plurality of pull-down units including the respective enabled pull-down resistors based on the second code.

2 . The memory device of claim 1 , wherein

a collective pull-up resistance of the respective pull-up resistors of the subset of pull-up units and/or a collective pull-down resistance of the respective pull-down resistors of the subset of pull-down units is substantially equivalent to the termination resistance.

3 . The memory device of claim 1 , wherein

the output driver further comprises at least one repair pull-up unit including at least one repair pull-up resistor and at least one repair pull-down unit including at least one repair pull-down resistor, and is configured to enable the subset of pull-up units from among the plurality of pull-up units including the respective pull-up resistors and the at least one repair pull-up unit based on the first code, and is configured to enable the subset of pull-down units from among the plurality of pull-down units including the respective pull-down resistors and the at least one repair pull-down unit based on the first code.

4 . The memory device of claim 3 , wherein

a number of the at least one repair pull-up unit is equal to or less than a number of pull-up units included in the subset of pull-up units, and a number of the at least one repair pull-down unit is equal to or less than a number of pull-down units included in the subset of pull-down units.

5 . The memory device of claim 3 , wherein

the at least one repair pull-up resistor and the at least one repair pull-down resistor comprise variable resistors, and

respective resistances of the variable resistors are configured to be adjusted based on the first code.

6 . The memory device of claim 1 , wherein

the second code includes a plurality of bits corresponding to the respective pull-up resistors, and a value of a bit that corresponds to the defective resistor from among the plurality of bits is different from values of other bits among the plurality of bits, and

the output driver is configured to disable one of the respective pull-up resistors that corresponds to the defective resistor and one of the respective pull-down resistors that is paired with the one of the respective pull-up resistors.

7 . The memory device of claim 1 , wherein

the second code includes a third code including a plurality of bits that correspond to the respective pull-up resistors and a fourth code including a plurality of bits that correspond to the respective pull-down resistors, and a value of a bit that corresponds to the defective resistor from among the plurality of bits is different from values of other bits among the plurality of bits, and

the output driver is configured to disable one of the respective pull-up resistors that corresponds to the defective resistor based on the third code, and is configured to disable one of the respective pull-down resistors that corresponds to the defective resistor based on the fourth code.

8 . The memory device of claim 1 , wherein

the plurality of pull-up units are coupled in parallel to each other, and the plurality of pull-down units are coupled in parallel to each other, and

the output driver is configured to increase a number of pull-up units included in the subset of pull-up units and a number of pull-down units included in the subset of pull-down units as resistance of the termination resistance indicated by the first code is reduced.

9 . A memory system comprising:

a memory device comprising a data input and output circuit including a plurality of pull-up units and a plurality of pull-down units and configured to output data signals through a data input and output pad, and a mode register configured to store a first code for indicating termination resistance of the memory device and a second code for disabling at least one of a plurality of resistors included in the data input and output circuit; and

a memory controller configured to receive a data signal among the data signals, determine whether the data signal indicates a defect, generate the second code responsive to determining that the data signal indicates the defect, provide the second code to the memory device, and generate and provide the first code to the memory device.

10 . The memory system of claim 9 , wherein

the memory controller is configured to determine whether the data signal indicates the defect based on whether a voltage level of the data signal is recognizable as a logic value “0” or “1”.

11 . The memory system of claim 9 , wherein

when the data signal has a defect, the memory controller is configured to change a value of the second code and provide the second code indicating the value that was changed to the memory device.

12 . The memory system of claim 9 , wherein

the plurality of pull-up units include pull-up resistors, the plurality of pull-down units include pull-down resistors, and the plurality of resistors include the pull-up resistors and the pull-down resistors.

13 . The memory system of claim 12 , wherein

when the data signal is not recognizable as a logic value “0”, the memory controller is configured to determine that defects are generated due to one or more of the pull-down resistors, and is configured to generate the second code, and

when the data signal is not recognizable as a logic value “1”, the memory controller is configured to determine that defects are generated due to one or more of the pull-up resistors, and is configured to generate the second code.

14 . The memory system of claim 12 , wherein

the second code includes a plurality of bits that correspond to the pull-up resistors, and a value of a bit among the plurality of bits that corresponds to a defective resistor is different from values of other bits among the plurality of bits, and

the memory device is configured to disable one of the pull-up resistors that corresponds to the defective resistor and one of the pull-down resistors that is paired with the one of the pull-up resistors.

15 . The memory system of claim 12 , wherein

the memory controller is configured to generate a parameter for setting termination resistance of the memory device, and

the memory device is configured to enable a subset of pull-up units that corresponds to a value of the parameter from among the plurality of pull-up units and a subset of pull-down units that corresponds to a value of the parameter from among the plurality of pull-down units, and is configured to output the data signal.

16 . The memory system of claim 15 , wherein

the plurality of pull-up units are coupled in parallel to each other, the plurality of pull-down units are coupled in parallel to each other, and

the memory device is configured to increase a number of pull-up units included in the subset of pull-up units and a number of pull-down units included in the subset of pull-down units as resistance value of the termination resistance indicated by the parameter is reduced.

17 . A method for operating a memory device, the method comprising:

writing or reading test data to or from a first in, first out (FIFO) portion of the memory device;

determining whether a data signal output by the memory device indicates a defect; and

enabling one or more resistors based on a code indicating the defect among a plurality of resistors included in the memory device; and

enabling a subset of pull-up units from among a plurality of pull-up units including the respective enabled one or more resistors and a subset of pull-down units from among a plurality of pull-down units including the respective enabled one or more resistors based on setting termination resistance of the memory device.

18 . The method of claim 17 , wherein the determining whether the data signal indicates the defect comprises:

determining whether the data signal indicates the defect based on whether a voltage level of the data signal is recognized as a logic value “0” or “1”.

19 . The method of claim 17 , wherein the enabling one or more resistors comprises:

disabling one or more resistors corresponding to the defect; and

enabling a number of one or more repair resistors based on a number of the one or more resistors that were disabled.

20 . The method of claim 17 , wherein the enabling one or more resistors comprises:

disabling one or more resistors corresponding to the defect; and

adjusting resistance of one or more repair resistors based on resistance of the one or more resistors that were disabled.