Nonvolatile memory device, storage device having the same, and testing method thereof

1 . A nonvolatile memory device, comprising:

at least one first universal interface bus (UIB) circuit coupled to a plurality of input/output (I/O) pads;

at least one second UIB circuit coupled to the plurality of I/O pads;

a core block comprising:

a first input terminal coupled to another block; and

a plurality of second input terminals coupled to a first output terminal of the at least one first UIB circuit and a second output terminal of the at least one second UIB circuit; and

at least one block configured to activate the at least one second UIB circuit.

2 . The nonvolatile memory device of claim 1 , wherein the nonvolatile memory device further comprises a memory cell region comprising:

a plurality of memory cells coupled to a plurality of wordlines and a plurality of bitlines; and

a peripheral region configured to control the memory cell region,

wherein the peripheral region comprises at least one circuit corresponding to the core block.

3 . The nonvolatile memory device of claim 1 , wherein the at least one first UIB circuit is configured to, in a scan mode, prevent activation of the first output terminal of the at least one first UIB circuit, and

wherein the at least one second UIB circuit is configured to, in the scan mode, activate the second output terminal of the at least one second UIB circuit.

4 . The nonvolatile memory device of claim 3 , wherein the at least one first UIB circuit and the at least one second UIB circuit are configured to determine the scan mode based on a scan mode activation signal.

5 . The nonvolatile memory device of claim 1 , wherein the at least one second UIB circuit is configured, in a UIB section, to:

receive test data; and

apply the test data to at least one input terminal of the plurality of second input terminals of the core block coupled to the second output terminal of the at least one second UIB circuit.

6 . The nonvolatile memory device of claim 5 , wherein the core block is configured to:

perform a scan test operation using the test data, based on a scan clock in a scan section.

7 . The nonvolatile memory device of claim 1 , wherein the at least one block is further configured to output an activation signal, and

wherein the nonvolatile memory device further comprises a scan mode output circuit configured to:

receive at least one of the activation signal or a scan mode activation signal; and

activate the at least one second UIB circuit based on the at least one of the activation signal or the scan mode activation signal.

8 . The nonvolatile memory device of claim 7 , wherein the scan mode output circuit comprises:

a logic circuit configured to perform an OR operation on the activation signal and the scan mode activation signal; and

an inverter configured to invert an output value of the logic circuit.

9 . The nonvolatile memory device of claim 8 , wherein the logic circuit is further configured to:

input the scan mode activation signal from at least one of an external pad or an internal circuit.

10 . The nonvolatile memory device of claim 1 , wherein the core block is configured to:

output result values of a scan test operation through a plurality of scan pads.