Semiconductor memory device and memory system
A semiconductor memory device includes a memory cell array configured to store data, and a control circuit configured to control a write operation of writing data into the memory cell array. In the write operation, the control circuit is configured to receive first data and second data including a parity bit, generate a parity bit for the first data, check whether the parity bit and the parity bit match with each other, and write the first data into the memory cell array.
1 . A semiconductor memory device comprising:
a memory cell array configured to store data; and
a control circuit configured to control a write operation to write data into the memory cell array, wherein
for control of the write operation, the control circuit is configured to:
receive first data and a first parity bit,
generate a second parity bit for the first data,
check whether the first parity bit and the second parity bit match each other, and
write second data into the memory cell array,
wherein
the first data includes the second data, and data for error detection generated for the second data.
2 . The semiconductor memory device according to claim 1 , wherein
for control of the write operation, the control circuit is configured to:
write the first data into the memory cell array, while writing the first parity bit into the memory cell array being omitted.
3 . The semiconductor memory device according to claim 1 , wherein
the control circuit is configured to check whether the first parity bit and the second parity bit match each other in parallel with a start-up of a voltage generation circuit for the write operation of writing the second data into the memory cell array.
4 . The semiconductor memory device according to claim 1 , wherein
when the first parity bit and the second parity bit do not match each other in the check operation,
the control circuit sets information representing that the first parity bit and the second parity bit do not match each other.
5 . The semiconductor memory device according to claim 1 , wherein
when the first parity bit and the second parity bit do not match each other in the check operation,
the control circuit receives the first data and the first parity bit again.
6 . The semiconductor memory device according to claim 1 , further comprising a parity check circuit configured to generate the second parity bit and check whether the first parity bit and the second parity bit match each other.
7 . The semiconductor memory device according to claim 1 , wherein
when the first parity bit and the second parity bit match each other in the check operation,
the control circuit executes the write operation of writing the second data into the memory cell array.
8 . The semiconductor memory device according to claim 1 , wherein
after ending the check on whether the first parity bit and the second parity bit match each other, the control circuit is configured to erase the first parity bit and the second parity bit.
9 . The semiconductor memory device according to claim 1 , wherein
calculation amount for generation of the data for error detection is higher than calculation amount for generation of the second parity bit.
10 . The semiconductor memory device according to claim 1 , wherein
error correction capability of the data for error detection is higher than error correction capability of the first parity bit.
11 . The semiconductor memory device according to claim 1 , wherein
the number of bits in the data for error detection is more than the number of bits in the first parity.
12 . The semiconductor memory device according to claim 1 , wherein
the semiconductor memory device is a NAND flash memory.
13 . The semiconductor memory device according to claim 1 , wherein
the memory cell array includes a memory cell capable to store one-bit data.
14 . The semiconductor memory device according to claim 1 , wherein
the memory cell array includes a memory cell capable to store three-bit data.
15 . The semiconductor memory device according to claim 1 , further comprising:
a first register to store the second data in an input/output circuit.
16 . The semiconductor memory device according to claim 15 , further comprising:
a second register to store the second data electrically provided between the first register and the memory cell array.
17 . The semiconductor memory device according to claim 16 , further comprising:
a sense amplifier to store the second data electrically provided between the second register and the memory cell array.
18 . The semiconductor memory device according to claim 1 , further comprising:
a storage circuit;
an ENOR gate; and
an AND gate.
19 . The semiconductor memory device according to claim 18 , further comprising:
the storage circuit stores one of bits of the first parity or the second parity, the one of bits of the first parity or the second parity are input to the ENOR gate, output of the ENOR gate is input to the AND gate.
20 . The semiconductor memory device according to claim 1 , further comprising:
a plurality of ENOR gates; and
an AND gate.
21 . The semiconductor memory device according to claim 20 , further comprising:
each of bits of the first parity and the second parity are input to each of the plurality of the ENOR gates respectively,
output of the plurality of the ENOR gates are input to the AND gate.
22 . The semiconductor memory device according to claim 1 , wherein each of bits of the first parity is sequentially input to a check circuit.
23 . The semiconductor memory device according to claim 21 , wherein the first parity bit is a transmission parity for the first data.
24 . The semiconductor memory device according to claim 1 , wherein the memory cell array includes a plurality of memory pillars located in a staggered arrangement.
25 . The semiconductor memory device according to claim 1 , wherein the memory cell array includes a plurality of memory pillars including a first insulating layer, a second insulating layer and a third insulating layer, the second insulating layer is disposed on a side surface of the first insulating layer, and the third insulating layer is disposed on a side surface of the second insulating layer.
26 . The semiconductor memory device according to claim 1 , wherein the memory cell array includes a bit line overlapping a memory pillar when viewed from a first direction intersecting to a substrate, the bit line is electrically connected to the memory pillar through a contact.
27 . A memory system comprising:
a semiconductor memory device including:
a memory cell array configured to store data, and
a control circuit configured to control a write operation to write data into the memory cell array; and
a controller configured to control the semiconductor memory device, wherein
for control of the write operation, the controller is configured to:
generate a first parity bit for the first data, and
transmit the first data, the first parity bit, and a command to instruct the write operation to the semiconductor memory device, and
the control circuit is configured to:
generate a second parity bit for the first data,
check the first parity bit and the second parity bit match each other, and
write second data into the memory cell array,
wherein
the first data includes the second data, and data for error detection generated for the second data.
28 . The memory system according to claim 27 , wherein
the control circuit is configured to:
check whether the first parity bit and the second parity bit match each other in parallel with a start-up of a voltage generation circuit for the write operation of writing the second data into the memory cell array.
29 . The memory system according to claim 27 , wherein
when the first parity bit and the second parity bit do not match each other in the check,
the control circuit sets first information representing that the first parity bit and the second parity bit do not match each other, and
when receiving the first information,
the controller is configured to transmit the first data and the first parity bit to the semiconductor memory device.
30 . The memory system according to claim 27 , further comprising:
a plurality of semiconductor memory devices including the semiconductor memory device.
31 . The memory system according to claim 27 , wherein the number of the semiconductor memory devices are four or more.
32 . A memory system comprising:
a semiconductor memory device including:
a memory cell array configured to store data, and
a control circuit configured to control a read operation of reading data from the memory cell array; and
a controller configured to control the semiconductor memory device, wherein
for the control of the read operation, the controller is configured to
transmit a first command to the semiconductor memory device, the control circuit is configured to:
execute a first read operation to read first data from the memory cell array according to the first command,
generate a first parity bit for the first data, and
execute a second read operation to transmit the first data and the first parity bit to the controller, and
the controller is configured to:
generate a second parity bit for the first data, and
check whether the first parity bit and the second parity bit match each other.
33 . The memory system according to claim 32 , wherein the first data includes second data, and data for error detection generated for the second data.
34 . The memory system according to claim 32 , wherein
when the first parity bit and the second parity bit do not match each other,
the controller is configured to transmit a second command to the semiconductor memory device, and
the control circuit is configured to transmit the first data and the first parity bit to the controller according to the second command.
35 . The memory system according to claim 34 , wherein
the first read operation takes longer the second read operation.
36 . The memory system according to claim 32 , wherein
when the first parity bit and the second parity bit match each other,
the controller is configured to
execute error checking on the second data using the data for error detection, and when the error checking fails,
transmit a third command to the semiconductor memory device, and
the control circuit is configured to
execute a third read operation different from the first read operation and the second read operation according to the third command, and
when the error checking is passed, the controller is configured to end the read operation.
37 . The memory system according to claim 36 , wherein
the first read operation takes longer than the second read operation, and
the third read operation takes longer than the first read operation.
38 . The memory system according to claim 34 , wherein
the semiconductor memory device further includes a register configured to store the first data,
in the first read operation, the first data read from the memory cell array is stored in the register, and
in the second read operation, the first data stored in the register is transmitted to the controller.
39 . The memory system according to claim 36 , wherein
in the third read operation, the first data is read from the memory cell array based on a plurality of pieces of read data obtained by a read operation using a plurality of read voltages, the plurality of read voltages includes a standard value and other values.