Methods, apparatus, and systems for a multi-band hybrid inductor-capacitor voltage-controlled oscillator

1 . An apparatus comprising:

an inverter having a first terminal and a second terminal coupled to an enable terminal;

a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inverter, the first terminal coupled to a supply terminal;

a second transistor having a control terminal, a first terminal, and a second terminal, the first terminal coupled to the second terminal of the first transistor;

an inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor;

a capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor;

a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inductor and the first terminal of the capacitor, the second terminal coupled to the second terminal of the inductor and the second terminal of the capacitor; and

a fourth transistor having a control terminal coupled to the enable terminal, a first terminal coupled to a ground terminal, and a second terminal coupled to the first terminal of the third transistor.

2 . The apparatus of claim 1 , the inverter is a first inverter, the inductor is a first inductor, the capacitor is a first capacitor, and the apparatus further includes:

a second inverter having a first terminal and a second terminal coupled to a tuning terminal;

a fifth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the second inverter, the first terminal coupled to the supply terminal;

a sixth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the first inductor and the first terminal of the first capacitor, the first terminal coupled to the second terminal of the fifth transistor;

a second inductor having a first terminal and a second terminal, the first terminal coupled to the second terminal of the sixth transistor;

a second capacitor having a first terminal coupled to the second terminal of the sixth transistor and the first terminal of the second inductor and a second terminal coupled to the second terminal of the second inductor;

a seventh transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the second terminal of the first inductor and the second terminal of the first capacitor, the second terminal coupled to the second terminal of the second inductor and the second terminal of the second capacitor; and

an eighth transistor having a control terminal coupled to the tuning terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the seventh transistor.

3 . The apparatus of claim 2 , wherein:

the first inductor and the first capacitor are configured to operate as a first LC tank circuit that is configured to generate a first oscillating signal based on an enable signal at the enable terminal; and

the second inductor and the second capacitor are configured to operate as a second LC tank circuit that is configured to generate a second oscillating signal based on a control signal at the tuning terminal, the second oscillating signal to adjust a frequency of the first oscillating signal based on a coupling factor between the first inductor and the second inductor.

4 . The apparatus of claim 2 , further including:

a ninth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the tuning terminal, the first terminal coupled to the supply terminal;

a tenth transistor having a control terminal coupled to the second terminal of the first inductor and the second terminal of the first capacitor, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the first terminal of the second inductor and the first terminal of the second capacitor;

an eleventh transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the first inductor and the first terminal of the first capacitor, the second terminal coupled to the second terminal of the second inductor and the second terminal of the second capacitor; and

a twelfth transistor having a control terminal coupled to the first terminal of the second inverter, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the eleventh transistor.

5 . The apparatus of claim 4 , wherein:

the first inductor and the first capacitor are configured to operate as a first LC tank circuit that is configured to generate a first oscillating signal when an enable signal at the enable terminal has a logic value of one; and

the second inductor and the second capacitor are configured to operate as a second LC tank circuit that is configured to:

generate a second oscillating signal out-of-phase with the first oscillating signal when a control signal at the tuning terminal has a logic value of one, the second oscillating signal to increase a frequency of the first oscillating signal based on a coupling factor between the first inductor and the second inductor; and

generate the second oscillating signal in-phase with the first oscillating signal when the control signal at the tuning terminal has a logic value of zero, the second oscillating signal to decrease the frequency of the first oscillating signal based on the coupling factor.

6 . The apparatus of claim 2 , wherein the first inductor is inductively coupled via a mutual inductance to the second inductor.

7 . The apparatus of claim 2 , wherein the second inductor is physically nested within the first inductor.

8 . An inductor-capacitor (LC) oscillator comprising:

a first inverter having a first terminal and a second terminal coupled to an enable terminal;

a first core including:

a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the first inverter, the first terminal coupled to a supply terminal;

a first LC tank circuit including a first inductor and a first capacitor, the first LC tank circuit having a first terminal and a second terminal across which a clock signal is to be measured; and

a second transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the enable terminal, the first terminal coupled to a ground terminal;

a second inverter having a first terminal and a second terminal coupled to a tuning terminal; and

a second core including:

a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the second inverter, the first terminal coupled to the supply terminal;

a fourth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the first LC tank circuit, the first terminal coupled to the second terminal of the third transistor;

a second LC tank circuit including a second inductor and a second capacitor, the second LC tank circuit having a first terminal and a second terminal, the first terminal coupled to the second terminal of the fourth transistor; and

a fifth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the second terminal of the first LC tank circuit, the second terminal coupled to the second terminal of the second LC tank circuit; and

a sixth transistor having a control terminal coupled to the tuning terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the fifth transistor, the first inductor being inductively coupled via a mutual inductance to the second inductor.

9 . The LC oscillator of claim 8 , wherein:

the first core is to generate a first oscillating signal based on an enable signal at the enable terminal; and

the second core is to generate a second oscillating signal based on a control signal at the tuning terminal, the second oscillating signal to adjust a frequency of the first oscillating signal based on a coupling factor between the first inductor of the first LC tank circuit and the second inductor of the second LC tank circuit.

10 . The LC oscillator of claim 8 , wherein:

the first core is to generate a first oscillating signal when an enable signal at the enable terminal has a logic value of one; and

the second core is to:

generate a second oscillating signal out-of-phase with the first oscillating signal when a control signal at the tuning terminal has a logic value of one, the second oscillating signal to increase a frequency of the first oscillating signal based on a coupling factor between the first inductor of the first LC tank circuit and the second inductor of the second LC tank circuit; and

generate the second oscillating signal in-phase with the first oscillating signal when the control signal at the tuning terminal has a logic value of zero, the second oscillating signal to decrease the frequency of the first oscillating signal based on the coupling factor.

11 . The LC oscillator of claim 8 , further including a buffer having a first terminal coupled to a clock terminal, a second terminal coupled to the first terminal of the first LC tank circuit, and a third terminal coupled to the second terminal of the first LC tank circuit.

12 . The LC oscillator of claim 8 , wherein the second inductor is physically nested within the first inductor.

13 . The LC oscillator of claim 8 , wherein an inductance of the LC oscillator is adjustable based on a control signal at the tuning terminal.

14 . A phase-locked loop (PLL) oscillator comprising:

a phase comparator circuit having a terminal;

a filter circuit having a first terminal and a second terminal coupled to the terminal of the phase comparator circuit; and

an inductor-capacitor (LC) voltage-controlled oscillator (VCO) including:

an inverter having a first terminal and a second terminal coupled to the first terminal of the filter circuit;

a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inverter, the first terminal coupled to a supply terminal;

a second transistor having a control terminal, a first terminal, and a second terminal, the first terminal coupled to the second terminal of the first transistor;

an inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the second transistor;

a capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor;

a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inductor and the first terminal of the capacitor, the second terminal coupled to the second terminal of the inductor and the second terminal of the capacitor; and

a fourth transistor having a control terminal coupled to the first terminal of the filter circuit, a first terminal coupled to a ground terminal, and a second terminal coupled to the first terminal of the third transistor.

15 . The PLL oscillator of claim 14 , wherein the PLL oscillator includes a tuning terminal, the inverter is a first inverter, the inductor is a first inductor, the capacitor is a first capacitor, and the LC VCO further includes:

a second inverter having a first terminal and a second terminal coupled to the tuning terminal of the PLL oscillator;

a fifth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the second inverter, the first terminal coupled to the supply terminal;

a sixth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the first inductor and the first terminal of the first capacitor, the first terminal coupled to the second terminal of the fifth transistor;

a second inductor having a first terminal and a second terminal, the first terminal coupled to the second terminal of the sixth transistor;

a second capacitor having a first terminal coupled to the second terminal of the sixth transistor and the first terminal of the second inductor and a second terminal coupled to the second terminal of the second inductor;

a seventh transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the second terminal of the first inductor and the second terminal of the first capacitor, the second terminal coupled to the second terminal of the second inductor and the second terminal of the second capacitor; and

an eighth transistor having a control terminal coupled to the tuning terminal, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the seventh transistor.

16 . The PLL oscillator of claim 15 , wherein:

the first inductor and the first capacitor are configured to operate as a first LC tank circuit that is configured to generate a first oscillating signal based on a signal at the first terminal of the filter circuit; and

the second inductor and the second capacitor are configured to operate as a second LC tank circuit that is configured to generate a second oscillating signal based on a control signal at the tuning terminal, the second oscillating signal to adjust a frequency of the first oscillating signal based on a coupling factor between the first inductor and the second inductor.

17 . The PLL oscillator of claim 15 , further including:

a ninth transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the tuning terminal, the first terminal coupled to the supply terminal;

a tenth transistor having a control terminal coupled to the second terminal of the first inductor and the second terminal of the first capacitor, a first terminal coupled to the second terminal of the ninth transistor, and a second terminal coupled to the first terminal of the second inductor and the first terminal of the second capacitor;

an eleventh transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the first inductor and the first terminal of the first capacitor, the second terminal coupled to the second terminal of the second inductor and the second terminal of the second capacitor; and

a twelfth transistor having a control terminal coupled to the first terminal of the second inverter, a first terminal coupled to the ground terminal, and a second terminal coupled to the first terminal of the eleventh transistor.

18 . The PLL oscillator of claim 17 , wherein:

the first inductor and the first capacitor are configured to operate as a first LC tank circuit that is configured to generate a first oscillating signal when an output signal at the first terminal of the filter circuit has a logic value of one; and

the second inductor and the second capacitor are configured to operate as a second LC tank circuit that is configured to:

generate a second oscillating signal out-of-phase with the first oscillating signal when a control signal at the tuning terminal has a logic value of one, the second oscillating signal to increase a frequency of the first oscillating signal based on a coupling factor between the first inductor and the second inductor; and

generate the second oscillating signal in-phase with the first oscillating signal when the control signal at the tuning terminal has a logic value of zero, the second oscillating signal to decrease the frequency of the first oscillating signal based on the coupling factor.

19 . The PLL oscillator of claim 15 , wherein the first inductor is inductively coupled via a mutual inductance to the second inductor.

20 . The PLL oscillator of claim 15 , wherein the second inductor is physically nested within the first inductor.