Integrated oscillator of low noise

Inventor: Chia-Liang (Leon) Lin (Fremont, CA)

Assignee: REALTEK SEMICONDUCTOR CORP.

H03B5/1212 H03B5/1209 H03B5/1218 H03B5/1221 H03B5/1228 H03B5/1296 H03B2200/0088 H03B2200/009

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Quick Facts

Patent No.: US 12695421
App. No.: 19/245,459
Granted: Jul 28, 2026
Kind: B1

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Abstract

An LC (inductor-capacitor) oscillator includes a first NMOS (n-channel metal oxide semiconductor) transistor, a first PMOS (p-channel metal oxide semiconductor) transistor, a second NMOS transistor, and a second PMOS transistor, wherein: the source of the first NMOS transistor is shorted to the source of the first PMOS transistor; the source of the second NMOS transistor is shorted to the source of the second PMOS transistor; the first NMOS transistor and the second NMOS transistor are cross coupled via a first gate inductor and a first drain inductor; the first and second PMOS transistors are cross coupled via a second gate inductor and a second drain inductor; the first NMOS transistor and the first PMOS transistor are coupled via a first gate capacitor and a first drain capacitor; and the second NMOS transistor and the second PMOS transistor are coupled via a second gate capacitor and a second drain capacitor.

Claims (34)

1 . An LC (inductor-capacitor) oscillator comprising:

a first NMOS (n-channel metal oxide semiconductor) transistor with source, gate, and drain connected to a first node, a second node, and a third node, respectively;

a second NMOS transistor with source, gate, and drain connected to a fourth node, a fifth node, and a sixth node, respectively;

a first PMOS (p-channel metal oxide semiconductor) transistor with source, gate, and drain connected to the first node, a seventh node, and an eighth node, respectively;

a second PMOS transistor with source, gate, and drain connected to the fourth node, a nineth node, and a tenth node, respectively;

a first gate inductor inserted between the second node and the fifth node with a center tap connected to a first gate bias node;

a second gate inductor inserted between the seventh node and the nineth node with a center tap connected to a second gate bias node;

a first drain inductor inserted between the third node and the sixth node with a center tap connected to a power supply node;

a second drain inductor inserted between the eighth node and the tenth node with a center tap connected to a ground node;

a first gate capacitor inserted between the second node and the seventh node;

a second gate capacitor inserted between the fifth node and the nineth node;

a first drain capacitor inserted between the third node and the eighth node; and

a second drain capacitor inserted between the sixth node and the tenth node.

2 . The LC oscillator of claim 1 , wherein the first gate inductor is strongly coupled to the second drain inductor, and the second gate inductor is strongly coupled to the first drain inductor.

3 . The LC oscillator of claim 1 , wherein the first gate inductor is coupled, at least moderately, to the second gate inductor, and the first drain inductor is coupled, at least moderately, to the second drain inductor.

4 . The LC oscillator of claim 1 being integrated and laid out upon a multi-layer planar structure and symmetrical with respect to a plane of symmetry that is perpendicular to the multi-layer planar structure.

5 . The LC oscillator of claim 4 , wherein the first gate inductor and the second gate inductor are configured as two outer half rings laid out on opposite sides of a central line that is perpendicular to the plane of symmetry, while the first drain inductor and the second drain inductor are configured as two inner half rings laid out on opposite sides of the central line.

6 . The LC oscillator of claim 5 , wherein the source of the first NMOS transistor and the source of the first PMOS transistor are laid out around the central line and directly shorted at the first node, while the source of the second NMOS transistor and the source of the second PMOS transistor are laid out around the central line and directly shorted at the fourth node.

7 . An LC (inductor-capacitor) oscillator comprising a first NMOS (n-channel metal oxide semiconductor) transistor, a first PMOS (p-channel metal oxide semiconductor) transistor, a second NMOS transistor, and a second PMOS transistor, wherein:

source of the first NMOS transistor is shorted to source of the first PMOS transistor;

source of the second NMOS transistor is shorted to source of the second PMOS transistor;

gate of the first NMOS transistor links to gate of the second NMOS transistor through a first gate inductor, of which a center tap connects to a first gate bias node;

gate of the first PMOS transistor links to gate of the second PMOS transistor through a second gate inductor, of which a center tap connects to a second gate bias node;

drain of the first NMOS transistor links to drain of the second NMOS transistor through a first drain inductor, of which a center tap connects to a power supply node;

drain of the first PMOS transistor links to drain of the second PMOS transistor through a second drain inductor, of which a center tap connects to a ground node;

the gate of the first NMOS transistor links to the gate of the first PMOS transistor through a first gate capacitor;

the gate of the second NMOS transistor links to the gate of the second PMOS transistor through a second gate capacitor;

the drain of the first NMOS transistor links to the drain of the first PMOS transistor through a first drain capacitor;

the drain of the second NMOS transistor links to the drain of the second PMOS transistor through a second drain capacitor;

the first gate inductor is strongly coupled to the second drain inductor; and

the second gate inductor is strongly coupled to the first drain inductor.

8 . The LC oscillator of claim 7 being integrated and laid out upon a multi-layer planar structure and symmetrical with respect to a plane of symmetry that is perpendicular to the multi-layer planar structure.

9 . The LC oscillator of claim 8 , wherein the first gate inductor and the second gate inductor are configured as two outer half rings laid out on opposite sides of a central line that is perpendicular to the plane of symmetry, while the first drain inductor and the second drain inductor are configured as two inner half rings laid out on opposite sides of the central line.

10 . The LC oscillator of claim 9 , wherein the source of the first NMOS transistor and the source of the first PMOS transistor are laid out around the central line and directly shorted, while the source of the second NMOS transistor and the source of the second PMOS transistor are laid out around the central line and directly shorted.