Power amplifier systems with frequency response compensation
A power amplification system is provided comprising: a power amplifier circuit, the power amplifier circuit including a plurality of transistors; and a frequency response compensation circuit for providing a plurality of values of capacitance. The frequency response compensation circuit having at least one tuning capacitor. Each of the at least one tuning capacitors is coupled to a tuning switch for regulating the current path to and/or from the corresponding capacitor to control the value of the capacitance provided by the frequency response compensation circuit. The frequency response compensation circuit is coupled to at least two of the transistors of the power amplifier circuit. The frequency response compensation circuit is configured to reduce variation over frequency of a load impedance of the power amplification system. A wireless device comprising such a power amplification system is also provided. A wireless module comprising such a power amplification system is also provided.
1 . A power amplification system comprising:
a power amplifier circuit, the power amplifier circuit including at least two differential transistors and at least one capacitor connected to the at least two differential transistors; and
a frequency response compensation circuit for providing a plurality of values of capacitance, the frequency response compensation circuit including at least one tuning capacitor coupled to a tuning switch to control a value of the capacitance provided by the frequency response compensation circuit, the tuning capacitor coupled in parallel with the at least one capacitor, the frequency response compensation circuit further coupled to the at least two differential transistors of the power amplifier circuit, and the frequency response compensation circuit configured to reduce variation over frequency of a load impedance of the power amplification system.
2 . The power amplification system of claim 1 wherein at least one of the at least two differential transistors is a heterojunction bipolar transistor.
3 . The power amplification system of claim 1 wherein the power amplifier circuit comprises a push-pull amplifier.
4 . The power amplification system of claim 3 wherein the push-pull amplifier includes a transformer balun.
5 . The power amplification system of claim 1 wherein the at least one capacitor connected to the differential transistors is connected to drains or collectors of two of the differential transistors.
6 . The power amplification system of claim 1 wherein the frequency response compensation circuit is coupled to a collector of at least one of the at least two the differential transistors.
7 . The power amplification system of claim 1 wherein the frequency response compensation circuit is couple to an an emitter of at least one of the at least two the differential transistors.
8 . The power amplification system of claim 1 wherein a capacitance of the power amplifier circuit is dependent on one or more of: a value of the at least one capacitor connected to the at least two differential transistors, a value of the capacitance provided by the frequency response compensation circuit, whether the at least one capacitor connected to the at least two differential transistors and the frequency response compensation circuit is connected in parallel or in series, and whether the tuning switch is on or off.
9 . The power amplification system of claim 1 wherein the frequency response compensation circuit provides low capacitance having a value close to zero when the tuning switch is off.
10 . The power amplification system of claim 1 wherein, when the tuning switch is off, the frequency response compensation circuit does not provide additional capacitance to the power amplifier circuit, and the power amplifier circuit has an impedance value that is suitable for operation at a higher frequency band.
11 . The power amplification system of claim 1 wherein, when the tuning switch is on, the frequency response compensation circuit provides additional capacitance to the power amplifier circuit that causes an on-resistance of the tuning switch at a lower frequency band to decrease and power-added efficiency of the power amplification system at the lower frequency band to increase.
12 . The power amplification system of claim 1 wherein the tuning switch of the frequency response compensation circuit enables control of the capacitance of the amplifier circuit.
13 . The power amplification system of claim 1 wherein the frequency response compensation circuit is configured to improve the power-added efficiency of the power amplification system.
14 . The power amplification system of claim 1 wherein the tuning switch is a FET switch.
15 . The power amplification system of claim 1 wherein the power amplification system comprises and/or is connected to one or more power amplifier components configured to provide at least one of advanced power tracking and envelop tracking.
16 . The power amplification system of claim 1 wherein one or more parts of the frequency response compensation circuit are controlled by a CMOS control, the CMOS control being configured receive band and/or power mode controls over a MIPI digital interface.
17 . The power amplification system of claim 1 comprising an output power control circuit for providing a plurality of values of capacitance, the output power control circuit having at least one load control capacitor coupled to a load control switch to control the value of the capacitance provided by the output power control circuit, and a balun coupled to the power amplifier circuit and to the output power control circuit.
18 . The power amplification system of claim 1 wherein at least one of the at least two transistors is a heterojunction bipolar transistor.
19 . A wireless device comprising:
a memory;
a user interface;
a baseband sub-system;
a transceiver;
a power management component; and
a power amplification system, the power amplification system including a power amplifier circuit having at least two differential transistors and at least one capacitor connected to the at least two differential transistors and a frequency response compensation circuit for providing a plurality of values of capacitance, the frequency response compensation circuit having at least one tuning capacitor coupled in parallel with the at least one capacitor and to a tuning switch to control a value of the capacitance provided by the frequency response compensation circuit, the frequency response compensation circuit further coupled to the at least two differential transistors of the power amplifier circuit, and the frequency response compensation circuit configured to reduce variation over frequency of a load impedance of the power amplification system.
20 . A wireless module comprising:
a packaging substrate;
one or more surface-mount devices;
a duplexer assembly;
a front-end power management integrated circuit;
a match component;
an antenna switch module; and
a power amplifier assembly including a power amplification system, the power amplification system having a power amplifier circuit, the power amplifier circuit including at least two differential transistors and at least one capacitor connected to the at least two differential transistors, a frequency response compensation circuit for providing a plurality of values of capacitance, the frequency response compensation circuit having at least one tuning capacitor coupled in parallel with the at least one capacitor and to a tuning switch to control a value of the capacitance provided by the frequency response compensation circuit, the frequency response compensation circuit further coupled to the at least two differential transistors of the power amplifier circuit, and the frequency response compensation circuit being configured to reduce variation over frequency of a load impedance of the power amplification system.