IP Library › Granted Patent US 12695451

Granted Patent B2

US 12695451 · App. 18/759,630 · Granted Jul 28, 2026

High-speed dynamic-impedance digital CMOS gate drivers for wide band-gap power devices

Inventor: Siddharth Dutta (San Jose, CA)

Assignee: Kinetic Technologies International Holdings LP

H03K19/0005 H03K19/018571

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Quick Facts

Patent No.: US 12695451
App. No.: 18/759,630
Granted: Jul 28, 2026
Kind: B2

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Abstract

One aspect disclosed features an apparatus comprising: an input buffer configured to receive an input voltage pulse as an input, and to output, responsive to a leading edge of the input voltage pulse, a logic high voltage pulse at a first output of the input buffer and a logic low voltage pulse at a second output of the input buffer; an array of L active pull-up devices electrically coupled between a positive supply rail and an output node, each active pull-up device driven by the logic high voltage pulse as modulated by a corresponding bit of a series of N first L-bit binary words; and an array of L active pull-down devices electrically coupled between a negative supply rail and the output node, each active pull-down device driven by the logic low voltage pulse as modulated by a corresponding bit of a series of M second L-bit binary words.

Claims (76)

1 . An apparatus comprising:

an input buffer configured to receive an input voltage pulse as an input, and to output, responsive to a leading edge of the input voltage pulse, a logic high voltage pulse at a first output of the input buffer and a logic low voltage pulse at a second output of the input buffer;

an array of L active pull-up devices electrically coupled between a positive supply rail and an output node, each active pull-up device driven by the logic high voltage pulse as modulated by a corresponding bit of a series of N first L-bit binary words;

an array of L active pull-down devices electrically coupled between a negative supply rail and the output node, each active pull-down device driven by the logic low voltage pulse as modulated by a corresponding bit of a series of M second L-bit binary words;

an array of L first switches respectively coupled to the array of L active pull-up devices and controlled by a respective bit of each of the first L-bit binary words; and

an array of L second switches respectively coupled to the array of L active pull-down devices and controlled by a respective bit of each of the second L-bit binary words,

wherein the series of N first L-bit binary words comprises at least two different first L-bit binary words that are applied at different times during the logic high voltage pulse, and

wherein the series of M second L-bit binary words comprises at least two different second L-bit binary words that are applied at different times during the logic low voltage pulse.

2 . The apparatus of claim 1 , wherein each active pull-up device comprises:

a low-voltage active pull-up device electrically coupled to the positive supply rail; and

a high-voltage active pull-up device electrically coupled between the low-voltage active pull-up device and the output node.

3 . The apparatus of claim 2 , wherein:

the low-voltage active pull-up device is driven by a respective bit of the first L-bit binary words; and

the high-voltage active pull-up device is biased at a predetermined bias voltage below a voltage of the positive supply rail.

4 . The apparatus of claim 3 , wherein:

the low-voltage active pull-up device is a first PMOS transistor; and

the high-voltage active pull-up device is a second PMOS transistor.

5 . The apparatus of claim 4 , wherein:

a source of the first PMOS transistor is electrically coupled to the positive supply rail;

a drain of the first PMOS transistor is electrically coupled to a source of the second PMOS transistor; and

a drain of the second PMOS transistor is electrically coupled to the output node.

6 . The apparatus of claim 5 , wherein:

a gate of the first PMOS transistor is driven by a respective bit of the first L-bit binary words; and

a gate of the second PMOS transistor is biased at the predetermined bias voltage below the voltage of the positive supply rail.

7 . The apparatus of claim 1 , wherein each active pull-down device comprises:

a low-voltage active pull-down device electrically coupled to the negative supply rail; and

a high-voltage active pull-down device electrically coupled between the low-voltage active pull-down device and the output node.

8 . The apparatus of claim 7 , wherein:

the low-voltage active pull-down device is driven by a respective bit of the second L-bit binary words; and

the high-voltage active pull-down device is biased at a predetermined bias voltage above a voltage of the negative supply rail.

9 . The apparatus of claim 8 , wherein:

the low-voltage active pull-down device is a first NMOS transistor; and

the high-voltage active pull-down device is a second NMOS transistor.

10 . The apparatus of claim 9 , wherein:

a source of the first NMOS transistor is electrically coupled to the negative supply rail;

a drain of the first NMOS transistor is electrically coupled to a source of the second NMOS transistor; and

a drain of the second NMOS transistor is electrically coupled to the output node.

11 . The apparatus of claim 10 , wherein:

a gate of the first NMOS transistor is driven by a respective bit of the second L-bit binary words; and

a gate of the second NMOS transistor is biased at the predetermined bias voltage above the voltage of the negative supply rail.

12 . An electronic device comprising:

a transistor; and

a driver coupled to the transistor and configured to drive the transistor, wherein the driver comprises: