Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.
1 . An apparatus comprising:
a memory controller configured to enable ZQ stop to halt a ZQ calibration operation by providing a mode register write command to a memory of a plurality of memories coupled to an external resistance, the mode register write command configured to set a bit in a mode register of the memory.
2 . The apparatus of claim 1 , wherein the mode register write command is configured to enable ZQ stop by setting a value of the bit to 1.
3 . The apparatus of claim 1 , wherein the memory controller is configured to provide a second mode register write command to set the bit in the mode register to resume normal operation of ZQ calibration.
4 . The apparatus of claim 3 , wherein the second mode register write command is configured to set a value of the bit to 0.
5 . The apparatus of claim 1 , wherein the bit comprises operand 1 (OP[1]) of the mode register.
6 . The apparatus of claim 1 , wherein the memory controller is configured to provide a ZQ calibration command.
7 . A method comprising:
providing, from a memory controller to a memory device, a mode register write command to set at least one bit in a mode register to enable ZQ stop to halt a ZQ calibration operation for one or more programmable termination resistances; and
causing the ZQ calibration operation to be halted when ZQ stop is enabled, wherein the ZQ calibration operation is performed by a memory device of a set of memory devices coupled to an external resistor.
8 . The method of claim 7 , wherein the mode register write command sets the at least one bit to 1 to enable ZQ stop.
9 . The method of claim 7 , further comprising:
providing, from the memory controller to the memory device, a second mode register write command to set the at least one bit to disable ZQ stop.
10 . The method of claim 9 , wherein the second mode register write command sets the at least one bit to 0 to indicate normal operation of ZQ calibration.
11 . The method of claim 7 , wherein the at least one bit comprises operand 1 (OP[1]) of the mode register.