Single comparator based comparison of an input voltage against multiple reference voltages

1 . A comparison circuit comprising:

a comparator to compare a comparator input with a comparator reference and generate a comparator output;

a mode selector to generate as a mode value, a first logic value if an input voltage is below a mid-voltage and a second logic value otherwise, wherein said mid-voltage is between a first reference voltage and a second reference voltage of interest, wherein said first reference voltage is lower than said second reference voltage;

a first branch coupled to receive said input voltage at a first node, and generate a first voltage drop relative to said input voltage at a second node, wherein said first voltage drop approximately equals a difference between said first reference voltage and said comparator reference;

a second branch coupled to receive said input voltage at said first node, and generate a second voltage drop relative to said input voltage at a third node, wherein said second voltage drop approximately equals a difference between said second reference voltage and said comparator reference;

a selection circuit to couple one of said second node or said third node as said comparator input according to said mode value,

wherein said mode value indicates whether said comparator output represents comparison with respect to said first reference voltage or said second reference voltage, and said comparator output indicates whether said input voltage is above or below a specific one of said first reference voltage or said second reference voltage compared with.

2 . The comparison circuit of claim 1 , wherein said first branch comprises a first resistor and a first switch coupled in series, wherein a first current flowing through said first resistor generates said first voltage drop,

wherein said second branch comprises a second resistor and a second switch coupled in series, wherein a second current flowing through said second resistor generates said second voltage drop,

wherein said selection circuit turns on only one of said first switch and said second switch based on said mode value.

3 . The comparison circuit of claim 2 , wherein said mode selector comprises:

a third resistor and a third current source in series with said first node to together generate a voltage drop equaling said mid-voltage relative to said input voltage at a fourth node; and

a first inverter connected to said fourth node to generate said mode value.

4 . The comparison circuit of claim 3 , wherein said selection circuit comprises:

a second inverter coupled in series to said first inverter,

wherein an output of said second inverter is coupled to said first switch, and an output of said first inverter is coupled to said second switch.

5 . The comparison circuit of claim 4 , wherein said input voltage is an instantaneous voltage of an input signal.

6 . The comparison circuit of claim 2 , wherein said both of said first current and said second current are generated by a single current source, said comparison circuit further comprising a logic block,

wherein said single current source is operable to generate current of a magnitude determined by a value set by said logic block, said logic block setting said value based on said mode value,

wherein said logic block sets said value to a first value to cause said single current source to generate said first current, thereby forming said first voltage drop across said first resistor, and

wherein said logic block sets said value to a second value to cause said single current source to generate said second current, thereby forming said second voltage drop across said second resistor.

7 . The comparison circuit of claim 6 , further comprising a blanking circuit, said blanking circuit to receive said mode value as an input and to generate a blanking pulse.

8 . The comparison circuit of claim 7 , wherein said logic block receives said comparator output, said mode value and said blanking pulse as respective inputs, said logic block to process said respective inputs to generate a first output signal, a second output signal, a third output signal and a fourth output signal,

wherein if said instantaneous voltage of said input signal is less than a first trip-point voltage, said logic block sets each of said first output signal and said second output signal to a first logic state, and each of said third output signal and said fourth output signal to a second logic state,

wherein if said instantaneous voltage of said input signal is between said first trip-point voltage and a second trip-point voltage, said logic block sets said second output signal to a first logic state, and each of said first output signal, said third output signal and said fourth output signal to said second logic state,

wherein if said instantaneous voltage of said input signal is between a third trip-point voltage and a fourth trip-point voltage, said logic block sets each of said first output signal, said second output signal and said third output signal to said second logic state, and said fourth output signal to said first logic state,

wherein if said instantaneous voltage of said input signal is greater than a fourth trip-point voltage, said logic block sets each of said first output signal and said second output signal to said second logic state, and each of said third output signal and said fourth output signal to said first logic state, and

wherein if said instantaneous voltage of said input signal is between said second trip-point voltage and a third trip-point voltage, said logic block sets all of said first output signal, said second output signal, said third output signal and said fourth output signal to said second logic state.

9 . The comparison circuit of claim 8 , wherein said blanking pulse is used by said logic block internally to ensure that each of said first output signal, said second output signal, said third output signal and said fourth output signal are generated only after switching transients due to switching between said first branch and said second branch have died out.

10 . A power stage of a switching converter comprising:

a high-side switch and a low-side switch coupled in series between a supply source and a constant reference potential, said supply source providing an input voltage, said high-side switch and said low-side switch respectively operated by a first drive signal and a second drive signal, said first drive signal and said second drive signal to be respectively ON to drive respective currents through an inductor in a first interval and a second interval;

a gate driver to generate said first drive signal and said second drive signal based on a control signal received from a phase controller, wherein said control signal is received with a first logic level in said first interval and with a second logic level in said second interval; and

a voltage-sense block comprising:

a comparator to compare a comparator input with a comparator reference and generate a comparator output, said comparator output to have a first output value when said comparator input is less than said comparator reference and a second output value otherwise;

a mode selector to generate as a mode value, a first logic value if said input voltage is below a mid-voltage and a second logic value otherwise, wherein said mid-voltage is between a first reference voltage and a second reference voltage of interest, wherein said first reference voltage is lower than said second reference voltage;

a first branch coupled to receive said input voltage at a first node, and generate a first voltage drop relative to said input voltage at a second node, wherein said first voltage drop approximately equals a difference between said first reference voltage and said comparator reference;

a second branch coupled to receive said input voltage at said first node, and generate a second voltage drop relative to said input voltage at a third node, wherein said second voltage drop approximately equals a difference between said second reference voltage and said comparator reference; and

a switching circuit to couple one of said second node or said third node as said comparator input according to said mode value,

wherein said mode value indicates whether said comparator output represents comparison with respect to said first reference voltage or said second reference voltage, and said comparator output indicates whether said input voltage is above or below a specific one of said first reference voltage or said second reference voltage compared with.

11 . The power stage of claim 10 , further comprising:

a logic block to send to said gate driver, a first signal when said mode value equals said first logic value and said comparator output equals said first output value or when said mode value equals said second logic value and said comparator output equals said second output value, and a second signal otherwise,

wherein said gate driver generates said first drive signal and said second drive signal to both be OFF if said input voltage is determined to be either less than said first reference voltage or greater than said second reference voltage.

12 . The power stage of claim 11 , wherein said first branch comprises a first resistor and a first switch coupled in series, wherein a first current flowing through said first resistor generates said first voltage drop,

wherein said second branch comprises a second resistor and a second switch coupled in series, wherein a second current flowing through said second resistor generates said second voltage drop,

wherein said selection circuit turns on only one of said first switch and said second switch based on said mode value.

13 . The power stage of claim 12 , wherein both of said first current and said second current are generated by a single current source, said comparison circuit further comprising a logic block,

wherein said single current source is operable to generate current of a magnitude determined by a value set by said logic block, said logic block setting said value based on said mode value,

wherein said logic block sets said value to a first value to cause said single current source to generate said first current, thereby forming said first voltage drop across said first resistor, and

wherein said logic block sets said value to a second value to cause said single current source to generate said second current, thereby forming said second voltage drop across said second resistor.

14 . The power stage of claim 13 , further comprising a blanking circuit, said blanking circuit to receive said mode value as an input and to generate a blanking pulse.

15 . The power stage of claim 14 , wherein said logic block receives said comparator output, said mode value and said blanking pulse as respective inputs, said logic block to process said respective inputs to generate a first output signal, a second output signal, a third output signal and a fourth output signal,

wherein if said instantaneous voltage of said input signal is less than a first trip-point voltage, said logic block sets each of said first output signal and said second output signal to a first logic state, and each of said third output signal and said fourth output signal to a second logic state,

wherein if said instantaneous voltage of said input signal is between said first trip-point voltage and a second trip-point voltage, said logic block sets said second output signal to a first logic state, and each of said first output signal, said third output signal and said fourth output signal to said second logic state,

wherein if said instantaneous voltage of said input signal is between a third trip-point voltage and a fourth trip-point voltage, said logic block sets each of said first output signal, said second output signal and said third output signal to said second logic state, and said fourth output signal to said first logic state,

wherein if said instantaneous voltage of said input signal is greater than a fourth trip-point voltage, said logic block sets each of said first output signal and said second output signal to said second logic state, and each of said third output signal and said fourth output signal to said first logic state, and

wherein if said instantaneous voltage of said input signal is between said second trip-point voltage and a third trip-point voltage, said logic block sets all of said first output signal, said second output signal, said third output signal and said fourth output signal to said second logic state.

16 . The power stage of claim 15 , wherein said blanking pulse is used by said logic block internally to ensure that each of said first output signal, said second output signal, said third output signal and said fourth output signal are generated only after switching transients due to switching between said first branch and said second branch have died out.