Method for complex hardware development error mitigation via independent analog representation of digital data
A system an analog to digital converter (ADC) operatively connected to receive an analog input signal from an input line and to output a digital input signal. A processor is operatively connected to receive the digital input signal from the ADC and to output a digital control signal for controlling a physical system based on the digital input signal. A digital to analog converter (DAC) is operatively connected to receive a copy of the digital input signal put out from the processor, and to output an analog output signal indicative of the copy of the digital input signal put out from the processor. Comparison logic is operatively connected to receive the analog input signal from the input line, to receive the analog output signal from the DAC, and to output an error signal in response to a mismatch between the analog input signal and the analog output signal.
1 . A system comprising:
a separate input line for each of multiple components of an analog input signal;
an analog-to-digital converter (ADC) operatively connected to receive the multiple components of the analog input signal from the separate input lines and to output a digital input signal representative of the analog input signal;
a processor operatively connected to receive the digital input signal from the ADC and to output a digital control signal for controlling a physical system based on the digital input signal;
a digital-to-analog converter (DAC) operatively connected to receive a copy of the digital input signal from the processor and to output a corresponding analog output signal for each component of the analog input signal indicative of the copy of the digital input signal from the processor; and
comparison logic including:
a first signal conditioner operatively connected to receive the multiple components of the analog input signal from the separate input lines and output corresponding conditioned analog input signals;
a second signal conditioner operatively connected to receive the analog output signals from the DAC and to output corresponding conditioned analog output signals; and
for each component of the analog input signal:
a respective difference amplifier operatively connected to receive the corresponding conditioned analog input signal, to receive the corresponding conditioned analog output signal, and to output a difference signal; and
a respective window comparator operatively connected to receive the difference signal, to compare the difference signal to a predetermined window, and to output a respective error signal to a shared OR gate in response to the difference signal being outside the predetermined window;
wherein the shared OR gate is configured to output an error signal in response to any one or more of the respective error signals being input to the shared OR gate.
2 . The system as recited in claim 1 , wherein the processor is a microprocessor, digital signal processor (DSP) or field programmable gate array (FPGA).
3 . The system as recited in claim 1 , further comprising, for at least one of the separate input lines, an analog math component in a signal lane connecting the separate input line to the comparison logic, wherein the processor includes a math function that matches a math function of the analog math component.
4 . The system as recited in claim 1 , wherein the comparison logic includes a latch having a set input, a reset input, and an latch output, wherein the set input is operatively connected to receive the error signal from the shared OR gate, wherein the reset input is operatively connected to receive a reset command to reset the latch after clearing an error, and wherein the latch is configured to output a trip signal indicative of an error in the processor in response to receiving the error signal until receiving the reset command.
5 . The system as recited in claim 1 , wherein each of the multiple components of the analog input signal is an AC phase.
6 . They system as recited in claim 5 , wherein the system is a bus power control unit (BPCU) and wherein the physical system is a power bus aboard an aircraft.
7 . The system as recited in claim 1 , wherein the analog input signal is operatively connected to convey output from an aircraft sensor aboard an aircraft, and wherein the physical system is aboard the aircraft.
8 . The system as recited in claim 7 , wherein the sensor is an air data sensor, wherein the physical system is a gas turbine engine, and wherein the processor is configured to control performance parameters of the gas turbine engine based on feedback from the air data sensor.
9 . The system as recited in claim 7 , wherein the sensor is a voltage and/or current sensor connected to a point of regulation (POR) in an output line of a generator, and wherein the system is a generator control unit (GCU) in which the processor is configured to control performance parameters of the generator based on feedback from the voltage and/or current sensor.
10 . A method comprising:
receiving multiple components an analog input signal;
converting the multiple components of the analog input signal into a digital input signal;
processing the digital input signal to produce a control signal for controlling a physical parameter of an aircraft system;
converting the digital input signal by a processor into a corresponding analog output signal for each component of the analog input signal;
conditioning, with a first signal conditioner, the analog output signals into corresponding conditioned analog output signals;
converting, with a second signal conditioner, the multiple components of the analog input signal into corresponding conditioned analog input signals;
for each of the multiple components of the analog input signal:
comparing the corresponding conditioned analog input signal to the corresponding conditioned analog output signal using a respective difference amplifier;
comparing, by a respective window comparator operatively connected to receive a difference signal from the respective difference amplifier, the difference signal to a predetermined window; and
outputting a respective error signal from the respective window comparator to a shared OR gate in response to the difference signal being outside the predetermined window; and
outputting an error signal from the shared OR gate in response to any one or more of the respective error signals being input to the shared OR gate.
11 . The method as recited in claim 10 , wherein controlling the physical parameter of the aircraft system includes controlling a power bus.
12 . The method as recited in claim 10 , wherein the analog input signal is received from an air data sensor, and wherein controlling the physical parameter of the aircraft system includes controlling performance parameters of a gas turbine engine based on feedback from the air data sensor.
13 . The method as recited in claim 10 , wherein the analog input signal is received from a voltage and/or current sensor connected to a point of regulation (POR) in an output line of a generator, and wherein controlling the physical parameter of the aircraft system includes controlling performance parameters of the generator based on feedback from the voltage and/or current sensor.
14 . The method as recited in claim 10 , wherein the processor is a microprocessor, digital signal processor (DSP) or field programmable gate array (FPGA).
15 . The method as recited in claim 10 , further comprising:
performing a digital math function on the digital input signal; and
performing an analog math function on at least one of the multiple components of the analog input signal that matches the digital math function performed on the digital input signal.
16 . The method as recited in claim 10 , further comprising:
receiving the error signal from the shared OR gate at a set input of a latch; and
outputting a trip signal from the latch indicative of an error in the processor in response to receiving the error signal.
17 . The method as recited in claim 16 , further comprising:
receiving a reset command at a reset input of the latch; and
discontinuing to output the trip signal from the latch in response to receiving the reset command at the reset input of the latch.
18 . The method as recited in claim 10 , wherein each of the multiple components of the analog input signal is an AC phase.
19 . The method as recited in claim 11 , wherein the method is performed by a bus power control unit (BPCU).
20 . The method as recited in claim 13 , wherein the method is performed by a generator control unit (GCU).