Compensated digital-to-analog converter (DAC)

1 . An analog-to-digital converter (ADC) comprising:

N current-steering digital-to-analog converters (DACs), wherein the ADC is an N-order sigma delta ADC, and wherein N is a positive integer greater than 0;

wherein each of the N current steering DACs comprises:

first and second output terminals,

a first current source having a first terminal coupled to a supply voltage terminal, a second terminal, and a third terminal;

a first transistor having a first current path terminal coupled to the second terminal of the first current source, and a second current path terminal coupled to the first output terminal;

a second transistor having a first current path terminal coupled to the second terminal of the first current source, and a second current path terminal coupled to the second output terminal; and

a first circuit having a first terminal coupled to the third terminal of the first current source, and a second terminal coupled to the first current path terminal of the first transistor and the first current path terminal of the second transistor, the first circuit comprising a first capacitor coupled to the third terminal of the first current source at the first terminal of the first circuit.

2 . The ADC of claim 1 , wherein the first current path terminals of the first and second transistors correspond to an intermediate node, and wherein a first capacitance of the first capacitor is equal to or lower than a parasitic capacitance between the intermediate node and a reference terminal.

3 . The ADC of claim 1 , wherein the first circuit further comprises:

a second current source; and

a third transistor having a current path terminal coupled to the second current source and the first capacitor, and a control terminal coupled to the second terminal of the first circuit.

4 . The ADC of claim 3 , wherein the third transistor is an n-type transistor.

5 . The ADC of claim 3 , wherein the third transistor is a p-type transistor.

6 . The ADC of claim 1 , further comprising a third transistor having a current path coupled between the first current source and the first and second transistors.

7 . The ADC of claim 1 , wherein the first current source comprises a third transistor having a current path coupled to the first capacitor, and further coupled to current paths of the first and second transistors.

8 . The ADC of claim 7 , wherein the third transistor comprises a control terminal configured to receive a fixed bias voltage.

9 . The ADC of claim 1 , wherein N is equal to 2.

10 . The ADC of claim 1 , further comprising a comparator having first and second inputs, wherein:

the first output terminal of a first current steering DAC of the N current steering DACs is coupled to the first input of the comparator; and

the second output terminal of the first current steering DAC is coupled to the second input of the comparator.

11 . The ADC of claim 10 , wherein a first output of the comparator is coupled to a control terminal of the first transistor of the first current steering DAC, and wherein a second output of the comparator is coupled to a control terminal of the second transistor of the first current steering DAC.

12 . The ADC of claim 11 , wherein the first output of the comparator is coupled to a control terminal of the first transistor of a second current steering DAC of the N current steering DACs, and wherein a second output of the comparator is coupled to a control terminal of the second transistor of the second current steering DAC.

13 . The ADC of claim 1 , further comprising a transconductance amplifier having first and second inputs, wherein:

the first output terminal of a first current steering DAC of the N current steering DACs is coupled to the first input of the transconductance amplifier; and

the second output terminal of the first current steering DAC is coupled to the second input of the transconductance amplifier.

14 . The ADC of claim 13 , wherein a first output of the transconductance amplifier is coupled to the first output terminal of a second current steering DAC of the N current steering DACs, and wherein a second output of the transconductance amplifier is coupled to the second output terminal of the second current steering DAC.

15 . The ADC of claim 1 , further comprising a transconductance amplifier having first and second outputs, wherein:

the first output terminal of a first current steering DAC of the N current steering DACs is coupled to the first output of the transconductance amplifier; and

the second output terminal of the first current steering DAC is coupled to the second output of the transconductance amplifier.

16 . A current-steering digital-to-analog converter (DAC) comprising:

first and second output terminals;

a power supply terminal;

a first transistor having a current path coupled between the power supply terminal and a first intermediate node;

a second transistor having a current path coupled between the first intermediate node and a second intermediate node;

a third transistor having a current path coupled between the second intermediate node and the first output terminal;

a fourth transistor having a current path coupled between the second intermediate node and the second output terminal; and

a first circuit having a first terminal coupled to the first intermediate node and a second terminal coupled to the second intermediate node, the first circuit comprising a first capacitor coupled to the first intermediate node at the first terminal of the first circuit.

17 . The current-steering DAC of claim 16 , wherein a first capacitance of the first capacitor is equal to or lower than a parasitic capacitance between the second intermediate node and a reference node.

18 . The current-steering DAC of claim 16 , wherein the first capacitor is coupled between the first intermediate node and a third intermediate node, the current-steering DAC further comprising a fifth transistor having a current path coupled between the power supply terminal and the third intermediate node, and a control terminal coupled to the second intermediate node.

19 . The current-steering DAC of claim 16 , wherein the first circuit is configured to:

source current via the first capacitor to the first intermediate node when a first voltage at the second intermediate node increases; and

sink current via the first capacitor from the first intermediate node when the first voltage decreases.

20 . An analog-to-digital converter (ADC) comprising:

N current-steering digital-to-analog converters (DACs), wherein the ADC is an N-order sigma delta ADC, and wherein N is a positive integer greater than 0;

wherein each of the N current steering DACs comprises:

first and second output terminals;

a first current source;

a first circuit having a first capacitor coupled to the first current source;

a first transistor coupled between the first current source and the first output terminal; and

a second transistor coupled between the first current source and the second output terminal; and

a comparator having a first input coupled to the first output terminal of a first current-steering DAC of the N current-steering DACs, and a second input coupled to the second output terminal of the first current-steering DAC.