Low-latency data acquisition using sigma-delta modulators

1 . A device, comprising:

a cascade of integrators (COI) filter including an accumulator having an output and a decimator having an input coupled to the output of the accumulator, in which an output of the decimator is an output of the COI filter; and

a SINC filter including the accumulator and the decimator of the COI filter, the SINC filter further including a differentiator having an input coupled to the output of the decimator, in which an output of the differentiator is an output of the SINC filter; and

a multiplexer having an output and first and second inputs, the first input of the multiplexer coupled to the output of the COI filter, the second input of the multiplexer coupled to the output of the SINC filter.

2 . The device of claim 1 , further comprising a controller having an input coupled to the output of the multiplexer, the controller configured to:

receive a first signal from the output of the COI filter and a second signal from the output of the SINC filter;

determine a slope of an analog signal based on the first and second signals; and

use the slope to predict a digital value representative of the analog signal at time t.

3 . The device of claim 2 , wherein the controller is configured to use the second signal at the time t to determine a first value, use the first signal at a time prior to t to determine a second value, and determine the slope using the first and second values.

4 . The device of claim 2 , further comprising:

an analog-to-digital converter (ADC) configured to provide the COI and SINC filters with a digital bitstream representative of the analog signal; and

a counter configured to reset a capacitor in the ADC responsive to receiving a clock signal including a gap between consecutive pulses that exceeds a first threshold.

5 . The device of claim 4 , wherein the counter is configured to:

increment a counter value beyond a second threshold responsive to the gap; and

provide a reset signal responsive to the counter value exceeding the second threshold, the reset signal configured to reset the capacitor.

6 . The device of claim 4 , wherein the controller is configured to reset the capacitor prior to each use of the COI filter.

7 . The device of claim 1 , wherein the SINC filter is a third-order SINC filter, the SINC filter has an oversampling ratio of 64, and the COI filter has an oversampling ratio of 128.

8 . A device, comprising:

a processor; and

memory coupled to the processor and storing instructions executable by the processor, the instructions configured to cause the processor to:

receive, at time t, a first digital value based on a SINC filter operating on a digital bitstream representing an analog signal;

receive a second digital value based on a cascade of integrators (COI) filter operating on the digital bitstream;

determine a slope based on the first and second digital values; and

predict a third digital value based on the slope and on a filter output value of the SINC filter or the COI filter, the third digital value representative of the analog signal at the time t.

9 . The device of claim 8 , further including a digital filter coupled to the processor, the digital filter including the SINC filter and the COI filter, in which the SINC filter and the COI filter share an accumulator and a decimator.

10 . The device of claim 9 , wherein:

the accumulator includes an output and the decimator includes an input coupled to the output of the accumulator, in which an output of the decimator is an output of the COI filter,

the SINC filter further includes a differentiator having an input coupled to the output of the decimator, in which an output of the differentiator is an output of the SINC filter, and

a multiplexer having an output and first and second inputs, the first input of the multiplexer coupled to the output of the COI filter, the second input of the multiplexer coupled to the output of the SINC filter.

11 . The device of claim 8 , wherein the SINC filter is a 3rd order SINC filter and has an oversampling ratio (OSR) of a, and wherein the COI filter has an OSR of 2a.

12 . The device of claim 8 , further comprising an analog-to-digital converter (ADC) configured to provide the digital bitstream using the analog signal, the ADC including multiple capacitors.

13 . The device of claim 12 , wherein executing the instructions causes the processor to trigger a counter in the ADC to reset the multiple capacitors prior to each use of the COI filter.

14 . A system, comprising:

an analog-to-digital converter (ADC) configured to sample an analog signal and to provide a digital bitstream based on the analog signal, the ADC including a capacitor;

a counter configured to:

increment a counter value of the counter to exceed a threshold value based on a clock signal; and

provide a reset signal responsive to the counter value of the counter exceeding the threshold value, the reset signal configured to adjust a voltage of the capacitor; and

a controller coupled to the ADC and the counter, the controller configured to:

provide the clock signal to the counter;

receive a first digital value based on a SINC filter operating on the digital bitstream and a second digital value based on a cascade of integrators (COI) filter operating on the digital bitstream;

determine a slope based on the first and second digital values; and

predict a third digital value of the analog signal based on the slope.

15 . The system of claim 14 , wherein the controller further includes a digital filter, the digital filter including the SINC filter and the COI filter, in which the SINC filter and the COI filter share an accumulator and a decimator.

16 . The system of claim 15 , wherein the SINC filter is a 3 rd order SINC filter with an oversampling ratio of 64, and wherein the COI filter has an oversampling ratio of 128.

17 . The system of claim 14 , wherein the controller is configured to receive the first digital value from the SINC filter at a time t, and wherein the third digital value is representative of the analog signal at the time t.

18 . The system of claim 14 , wherein the counter includes an output and first and second inputs, the counter configured to:

receive a pulsed signal on the first input;

receive the clock signal on the second input;

reset the counter value based on rising and falling edges of the clock signal;

increment the counter value beyond the threshold value based on the pulsed signal and a gap in the clock signal; and

provide the reset signal on the output of the counter responsive to the counter value exceeding the threshold value.

19 . The system of claim 14 , wherein the capacitor is a first capacitor having first and second terminals, and wherein the system includes a first switch having first and second terminals, a second switch having first and second terminals, and a second capacitor having first and second terminals, in which the first terminal of the first switch is coupled to the first terminal of the first capacitor, the second terminal of the first switch is coupled to the first terminal of the second capacitor, the first terminal of the second switch is coupled to the second terminal of the first capacitor, and the second terminal of the second switch is coupled to the second terminal of the second capacitor, wherein the switches are configured to equalize voltages across the first and second capacitors responsive to the reset signal.

20 . The system of claim 14 , wherein the system includes:

a motor having an input;

a motor driver having an output coupled to the input of the motor and an input, the motor driver configured to receive the analog signal on the input of the motor driver and to drive the motor responsive to the analog signal.