Receiver equalizer circuit, transmitter equalizer circuit, and electronic device
A receiver equalizer circuit is described. The equalizer circuit includes a signal input, a first signal processing channel, a second signal processing channel, and a filter circuit. The first signal processing channel includes a first analog-to-digital converter and a first digital down-converter provided downstream of the first analog-to-digital converter. The second signal processing channel includes a second analog-to-digital converter and a second digital down-converter provided downstream of the second analog-to-digital converter. The filter circuit is connected to the signal processing channels downstream of the digital down-converters. Further, a transmitter equalizer circuit and an electronic device are described.
1 . A transmitter equalizer circuit, comprising:
a signal input, a first signal processing channel, a second signal processing channel, and a filter circuit, wherein the filter circuit is connected to the signal input,
the first signal processing channel comprising a first digital up-converter, and a first digital-to-analog converter provided downstream of the first digital up-converter, wherein the first digital up-converter is configured to up-convert a digital signal processed by the first signal-processing channel, thereby obtaining a first up-converted signal having a higher sample rate than the digital signal processed by the first signal-processing channel, and wherein the first digital-to-analog converter is configured to convert the first up-converted signal or a processed version of the first up-converted signal into a first analog signal,
the second signal processing channel comprising a second digital up-converter, and a second digital-to-analog converter provided downstream of the second digital up-converter, wherein the second digital up-converter is configured to up-convert a digital signal processed by the second signal-processing channel, thereby obtaining a second up-converted signal having a higher sample rate than the digital signal processed by the first signal-processing channel, and wherein the second digital-to-analog converter is configured to convert the second up-converted signal or a processed version of the second up-converted signal into a second analog signal, and
wherein the filter circuit is connected to the signal processing channels upstream of the digital up-converters.
2 . The transmitter equalizer circuit of claim 1 , wherein the filter circuit is configured to pre-equalize the digital signals processed by the signal-processing channels.
3 . The transmitter equalizer circuit of claim 2 , wherein the filter circuit is configured to pre-equalize the digital signals processed by the signal-processing channels such that cross talk between the signal processing channels and/or imbalances between the signal processing channels are/is removed.
4 . The transmitter equalizer circuit of claim 1 , wherein the filter circuit comprises a first filter sub-circuit being connected to the first signal processing channel, and wherein the filter circuit comprises a second filter sub-circuit being connected to the second signal processing channel.
5 . The transmitter equalizer circuit of claim 4 , wherein the first filter sub-circuit and the second filter sub-circuit are established as a complex-valued filter, respectively.
6 . The transmitter equalizer circuit of claim 4 , wherein the filter circuit comprises a splitter circuit being connected to each of the first filter sub-circuit and the second filter sub-circuit, wherein the splitter circuit is configured to forward a signal received via the signal input to the filter sub-circuits.
7 . The transmitter equalizer circuit of claim 1 , wherein the first signal processing channel is configured to process an in-phase signal, and wherein the second signal processing channel is configured to process a quadrature signal.
8 . An electronic device, the electronic device comprising a transmitter equalizer circuit according to claim 1 .
9 . The electronic device of claim 8 , wherein the electronic device is established as a measurement instrument.
10 . The electronic device of claim 8 , wherein the electronic device is established as a radio frequency (RF) receiver and/or as an RF transmitter.
11 . The transmitter equalizer circuit of claim 1 , wherein the first digital up-converter is configured to interpolate the digital signal processed by the first signal-processing channel by an interpolation factor to increase the sample rate of the digital signal processed by the first signal-processing channel, and
wherein the second digital up-converter is configured to interpolate the digital signal processed by the second signal-processing channel by the interpolation factor to increase the sample rate of the digital signal processed by the second signal-processing channel.