Scheduling method for LDPC decoding
Apparatuses, systems, and techniques to correct errors in information received from a plurality of fifth-generation new radio antennas. In at least one embodiment, codeword information is decoded by a plurality of variable (or vector) nodes and check nodes, where codewords and nodes are divided among processors to be performed in parallel.
1 . One or more processors comprising:
circuitry to perform error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
2 . The one or more processors of claim 1 , wherein the circuitry is further to:
perform error correction on a plurality of check nodes, wherein each of the plurality of check nodes corresponds to one or more of the plurality of variable nodes; and
update the per-thread copies of belief values for the plurality of variable nodes with one or more new values calculated by performing a set of instructions implementing the plurality of check nodes.
3 . The one or more processors of claim 1 , wherein each of the plurality of processing threads error corrects by updating per-thread local copies of belief values for variable nodes of the single 5G-NR codeword according to different portions of a parity check matrix.
4 . The one or more processors of claim 1 , wherein each variable node of the plurality of variable nodes comprises a global belief value corresponding to the single 5G-NR codeword and corresponding per-thread local belief values stored for the variable node by the plurality of processing threads.
5 . The one or more processors of claim 1 , wherein the circuitry is further to implement a check node to calculate a belief value indicating a likelihood that a variable node of the plurality of variable nodes has a specific value.
6 . The one or more processors of claim 1 , wherein the plurality of processing threads correspond to parallel processing units (PPUs).
7 . The one or more processors of claim 1 , wherein the single 5G-NR codeword has been encoded by a low density parity check (LDPC) coding scheme.
8 . A system comprising:
one or more processors to be configured to perform error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
9 . The system of claim 8 , further comprising memory to store:
the plurality of variable nodes, wherein the plurality of variable nodes comprise belief values corresponding to the single 5G-NR codeword; and
a set of instructions that, when performed, implement a plurality of check nodes to perform one or more error correction operations, wherein each check node corresponds to one or more variable nodes of the plurality of variable nodes.
10 . The system of claim 9 , wherein each variable node of the plurality of variable nodes comprises a global belief value corresponding to the single 5G-NR codeword and corresponding per-thread local belief values stored for the variable node by the plurality of processing threads.
11 . The system of claim 9 , wherein the one or more error correction operations calculate a belief value that indicates a likelihood that a variable node of the plurality of variable nodes indicates a value determined by a parity check matrix.
12 . The system of claim 8 , wherein each of the plurality of processing threads error corrects, at least in part, by updating corresponding per-thread copies of belief values for variable nodes of the single 5G-NR codeword according to different portions of a parity check matrix.
13 . The system of claim 12 , wherein each of the plurality of processing threads error corrects, at least in part, by iteratively updating respective per-thread copies of belief values for variable nodes of the single 5G-NR codeword.
14 . The system of claim 8 , wherein the plurality of processing threads correspond to PPUs.
15 . The system of claim 8 , wherein the single 5G-NR codeword has been received from a plurality of 5G new radio antennas and has been encoded by an LDPC coding scheme.
16 . A machine-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least:
perform error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
17 . The machine-readable medium of claim 16 , wherein the instructions, if performed by the one or more processors, further cause the one or more processors to at least:
store belief values corresponding to the single 5G-NR codeword in the plurality of variable nodes;
perform one or more operations by a plurality of check nodes, where each check node corresponds to one or more variable nodes of the plurality of variable nodes; and
calculate, for each check node of the plurality of check nodes, a belief value for each of the one or more variable nodes corresponding to the check node.
18 . The machine-readable medium of claim 17 , wherein the instructions, if performed by the one or more processors, further cause the one or more processors to store a master belief value in a master variable node of the plurality of variable nodes, and store per-thread local belief values in one or more other variable nodes.
19 . The machine-readable medium of claim 17 , wherein the instructions further cause the plurality of processing threads to perform the one or more operations for corresponding check nodes of the plurality of check nodes.
20 . The machine-readable medium of claim 16 , wherein the instructions further cause each of the plurality of processing threads to error correct, at least in part, by updating per-thread copies of belief values for variable nodes of the single 5G-NR codeword according to different portions of a parity check matrix.
21 . The machine-readable medium of claim 16 , wherein the instructions further cause each of the plurality of processing threads to error correct, at least in part, by updating per-thread copies of belief values for variable nodes of the single 5G-NR codeword.
22 . The machine-readable medium of claim 16 , wherein the plurality of processing threads correspond to PPUs.
23 . The machine-readable medium of claim 16 , wherein the single 5G-NR codeword has been received from a plurality of 5G new radio antennas and encoded by an LDPC coding scheme.
24 . A method, comprising:
performing error correction on a plurality of variable nodes of a single fifth generation new radio (5G-NR) codeword using a plurality of processing threads to process different per-thread copies of belief values corresponding to nodes of the single 5G-NR codeword in parallel.
25 . The method of claim 24 , further comprising:
storing belief values corresponding to the single 5G-NR codeword in the plurality of variable nodes;
performing one or more operations by a plurality of check nodes, where each check node corresponds to one or more variable nodes of the plurality of variable nodes; and
calculating, for each check node of the plurality of check nodes, a belief value for each of the one or more variable nodes corresponding to the check node.
26 . The method of claim 25 , further comprising:
storing a master belief value corresponding to the single 5G-NR codeword in a variable node of the plurality of variable nodes; and
storing per-thread local belief values in other variable nodes of the plurality of variable nodes.
27 . The method of claim 25 , further comprising causing the plurality of processing threads to perform the one or more operations for corresponding check nodes of the plurality of check nodes.
28 . The method of claim 24 , further comprising error correcting, at least in part, by updating per-thread copies of belief values for variable nodes of the single 5 G-NR codeword according to different portions of a parity check matrix using corresponding ones of the plurality of processing threads.
29 . The method of claim 24 , further comprising error correcting a subset of the single 5G-NR codeword iteratively by each of the plurality of processing threads.
30 . The method of claim 24 , wherein the plurality of processing threads correspond to PPUs, and each PPU includes one or more processing cores.
31 . The method of claim 24 , wherein the single 5G-NR codeword is received from a plurality of 5G new radio antennas and has been encoded by an LDPC coding scheme.
32 . The method of claim 24 , wherein the plurality of processing threads correspond to a plurality of processor pipelines of a graphics processing unit (GPU).
33 . The method of claim 24 , wherein error correcting the single 5G-NR codeword in parallel comprises:
performing a set of instructions to implement a plurality of check nodes to perform error correction of the single 5G-NR codeword in parallel, at least in part, by updating per-thread copies of belief values corresponding to variable nodes, wherein each of the plurality of check nodes corresponds to one or more variable nodes of the plurality of variable nodes.
34 . The method of claim 33 , wherein:
performing a set of instructions to implement a plurality of check nodes to perform error correction of the single 5G-NR codeword in parallel comprises sequential processing within each of the corresponding plurality of processing threads.