IP Library › Granted Patent US 12695607

Granted Patent B2

US 12695607 · App. 17/985,736 · Granted Jul 28, 2026

Integrated circuit protection using stacked dies

Inventors: James D. Wesselkamper (Albuquerque, NM); Thomas Paul Leboeuf (Sandia Park, NM); Steve E. Mcneil (Los Ranchos, NM); Jason J. Moore (Albuquerque, NM); James Anderson (Madison, AL)

Assignee: XILINX, INC.

H04L9/088 H10W42/405 H10W90/00 H10W90/722 H10W90/724

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Quick Facts

Patent No.: US 12695607
App. No.: 17/985,736
Granted: Jul 28, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

Stacked integrated circuit devices, chip packages and methods for operating a chip package are described herein that provide an increased level of backside protection from physical attacks that could compromise confidentiality or authentication of the integrated circuit device. In one example, a chip stack includes a sacrificial integrated circuit (IC) die stacked with a primary IC die. The sacrificial IC die includes a first split key information source. The primary IC die has security circuitry configured to generate an encryption key based at least in part on first split key information transmitted from the sacrificial IC die across a die-to-die interface to the primary IC die. Separation of the dies to probe or modify of the primary IC die would cause the destruction of split key information required to operate the functional circuitry of the primary IC die.

Claims (51)

1 . A chip stack, comprising:

first and second integrated circuit (IC) dies and a package substrate in a stacked configuration, wherein the second IC die is disposed between the first IC die and the package substrate;

a first entropy source distributed across the first and second IC dies; and

security circuitry disposed in the second IC die and configured to generate a first key that is unique to the chip stack based at least in part on a measure of entropy of the first entropy source;

wherein the first entropy source comprises a first routing, wherein a first portion of the first routing is disposed in the first IC die, a second portion of the first routing is disposed in the second IC die, and an interface between the first and second IC dies comprises a third portion of the first routing;

wherein the second portion of the first routing comprises routing residing in a metal layer of the second IC die that is closer to the package substrate and further from the first IC die than the security circuitry; and

wherein the chip stack further comprises:

a second entropy source comprising a first physical unclonable function (PUF) device disposed in the first IC die and coupled to the second IC die through the interface; and

first summation circuitry disposed in the second IC die, configured to output a first key signal based on a comparison of the measures of entropy of the first and second entropy sources the first PUF device; and

wherein the security circuitry comprises key assembly circuitry configured to generate the key based on the first key signal.

2 . The chip stack of claim 1 , further comprising:

first routing integrity circuitry disposed in the second IC die and configured to sense the measure of entropy of the first entropy source.

3 . The chip stack of claim 2 , wherein the first entropy source comprises one or more of a resistance, a capacitance, and an inductance.

4 . The chip stack of claim 2 , wherein the security circuitry comprises authentication circuitry configured to authenticate the chip stack based on the key.

5 . The chip stack of claim 1 , wherein the first entropy source further comprises:

a first physical unclonable function (PUF) device disposed in the first IC die and coupled to the first portion of the first routing.

6 . The chip stack of claim 5 , wherein the first PUF device comprises one or more of an oscillator, static random-access memory, a connection mesh, and non-volatile memory.

7 . The chip stack of claim 1 , further comprising:

a third entropy source comprising a second PUF device disposed in the first IC die and coupled to the second IC die through the interface; and

a fourth entropy source comprising a second routing;

wherein a first portion of the second routing is disposed in the first IC die, a second portion of the second routing is disposed in the second IC die, and the interface comprises a third portion of the second routing; and

wherein the second portion of the second routing comprises routing residing in the metal layer of the second IC die that is closer to the package substrate and further from the first IC die than the security circuitry;

second routing integrity circuitry disposed in the second IC die and configured to sense a measure of entropy of the fourth entropy source; and

second summation circuitry disposed in the second IC die, configured to output a second key signal based on a comparisons of a measure of entropy of the third entropy source and the measure of entropy of the fourth entropy source;

wherein the key assembly circuitry is configured to generate the key based further on the second key signal.

8 . The chip stack of claim 2 , wherein the second portion of the first routing is dead ended in the first IC die.

9 . A chip package, comprising:

first and second integrated circuit (IC) dies and a package substrate in a stacked configuration, wherein the second IC die is disposed between the first IC die and the package substrate;

a first entropy source comprising a first routing extending across an interface connecting the first and second IC dies, wherein a first portion of the first routing is disposed in the first IC die, a second portion of the first routing is disposed in the second IC die, and a third portion of the first routing is disposed in the interface;

first routing integrity circuitry disposed in the second IC die and coupled to the second portion of the first routing, wherein the first routing integrity circuitry is configured to output a measure of entropy of the first entropy source;

key assembly circuitry disposed in the second IC die routing, the key assembly circuitry configured to generate a key based at least in part on the measure of entropy of the first entropy source; and

authentication circuitry disposed in the second IC die configured to authenticate the chip package based on the key;

a first physical unclonable function (PUF) device disposed in the first IC; and

first summation circuitry disposed in the second IC die, configured to output a first key signal based on a comparison of measures of entropy of the first and second entropy sources;

10 . The chip package of claim 9 , wherein the first entropy source comprises one or more of a resistance, a capacitance, and an inductance.

11 . The chip package of claim 9 , wherein the second IC die is mounted directly to the first IC die.

12 . The chip package of claim 9 , wherein the first PUF device comprises one or more of a ring-oscillator, static random-access memory, a connection mesh, and non-volatile memory.

13 . An integrated circuit (IC) device, comprising:

first and second integrated circuit (IC) dies and a package substrate in a stacked configuration, wherein the second IC die is disposed between the first IC die and the package substrate;

first and second entropy sources, each distributed amongst the first and second IC dies;

a summation circuit disposed in the second IC die and configured to output a key signal based on measures of entropy of the first and second entropy sources; and

security circuitry configured to generate a key that is unique to the IC device based on the key signal;

wherein the summation circuit is further configured to output the key signal based on a comparison of the measures of entropy of the first and second entropy sources.

14 . The IC device of claim 13 , wherein:

the summation circuit is further configured to output the key signal based on a comparison of the measures of entropy of the first and second entropy sources to predefined criteria.

15 . The IC device of claim 13 , wherein the summation circuit comprises:

a logic function configured to output the key signal based on the measures of entropy of the first and second entropy sources.

16 . The IC device of claim 13 , wherein:

the first entropy source comprises a first routing, wherein a first portion of the first routing is disposed in the first IC die, a second portion of the first routing is disposed in the second IC die, and an interface between the first and second IC dies comprises a third portion of the first routing; and

the second portion of the first routing comprises routing residing in a metal layer of the second IC die that is closer to the package substrate and further from the first IC die than the security circuitry.