IP Library Granted Patent US 12695621
Granted Patent B2
US 12695621 · App. 18/795,461 · Granted Jul 28, 2026

Memory system

Inventor: Masahiro Kusaka (Kawasaki, JP)
Assignee: KIOXIA CORPORATION
H04L9/3247H04L9/14
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12695621
App. No.
18/795,461
Granted
Jul 28, 2026
Kind
B2
Abstract

A memory system includes a first storage; a second storage storing log information indicating a history of accesses to the first storage; a third storage storing a first private key and a first public key; and a processor configured to convert the log information into a first hash value by inputting the log information into a hash function, sign the first hash value using the first private key, and generate a first signature. The processor is further configured to convert the log information read from the second storage into a second hash value by inputting the log information into the hash function; and perform signature verification using the first public key paired with the first private key and the second hash value.

Claims (15)

1 . A memory system comprising:

a first storage;

a second storage storing log information indicating a history of accesses to the first storage;

a third storage storing a first private key and a first public key; and

a processor configured to convert the log information into a first hash value by inputting the log information to a hash function, sign the first hash value using a first private key, generate a first signature, and generate an aggregate signature by adding a plurality of the first signatures corresponding to a plurality of pieces of the log information, respectively, wherein

the processor is further configured to:

generate a first mapping by pairing the aggregate signature and a first point on an elliptic curve;

convert the plurality of pieces of log information into a plurality of second hash values, respectively, by inputting the plurality of pieces of log information to the hash function;

generate a second mapping by pairing a second encryption key obtained by using a first encryption key and the first point on the elliptic curve with the plurality of second hash values;

generate a third mapping by multiplying a plurality of the second mappings corresponding to the plurality of pieces of log information, respectively; and

compare the first mapping with the third mapping.

2 . The memory system according to claim 1 , wherein

the processor is further configured to:

transmit a first signal indicating that the log information has not been altered when the first mapping and the third mapping are equal; and

transmit a second signal indicating that the log information has been altered when the first mapping and the third mapping are different.