High speed TX topology with a common mode controlled serialization stage embedded in an output stage
A high-speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using NMOS transistors. In addition, the logic circuit is configured to be a desired voltage value (e.g., the output circuit's common mode) such that a switching point of the NMOS gm stage can be decreased and the gm stage can be activated within a reduced time.
1 . A transmitter comprising:
a serialization circuit configured to convert parallel data into serial data with one or more serialization stages;
a logic circuit electrically coupled to the serialization circuit and an output circuit, the logic circuit configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated NMOS based trans-conductance (gm) output stage of the output circuit; and
the output circuit configured to implement output stages to generate a signal based on the received input using n-channel metal oxide semiconductor (NMOS) field effect transistors, wherein:
a ground of the logic circuit is configured to be a desired voltage value so as to decrease a switching point of the gm output stage of the output circuit, such that the gm output stage can be activated within a reduced time,
the switching point is a threshold voltage value at which a NMOS transistor is turned on, and
the desired voltage value includes a common mode of the output circuit.
2 . The transmitter of claim 1 , wherein:
the serialization circuit includes a series of multiplexers in the one or more serialization stages,
the last serialization stage is a multiplexer having a plurality of inputs, and
the logic circuit is configured to connect a plurality of bits input from the last serialization stage to a plurality of gm stages through a plurality of logic functions.
3 . The transmitter of claim 2 , wherein the input of the last serialization stage is connected to the respective output stage with a relevant clock phase.
4 . The transmitter of claim 3 , wherein the serialization circuit and the output circuit are connected by the logic circuit in a way that reduces data load of the last serialization stage and increases operation speed of the transmitter.
5 . The transmitter of claim 1 , wherein each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.
6 . The transmitter of claim 1 , further comprising:
a data acquisition circuit configured to generate the parallel data in a plurality of data branches,
wherein the serialization circuit and the logic circuit are configured to convert the parallel data received from the plurality of data branches into a single sequence of data.
7 . The transmitter of claim 1 , wherein the transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return-to-zero (NRZ) transmitter, or other types of transmitters.
8 . The transmitter of claim 1 , wherein the logic circuit is connected to an external reference voltage and adjusted to enable a current source to operate in saturation.
9 . A method for configuring and implementing a transmitter, comprising:
receiving, by a serialization circuit, data in parallel from a plurality of data branches, the serialization circuit including one or more serialization stages;
connecting each input of a last stage of the one or more serialization stages, via a respective logic function of a logic circuit, to a respective dedicated NMOS based trans-conductance (gm) output stage of an output circuit; and
implementing, by the output circuit, output stages to generate a signal based on the received input using n- channel metal oxide semiconductor (NMOS) field effect transistors, wherein:
a ground of the logic circuit is configured to be a desired voltage value so as to decrease a switching point of the gm output stage of the output circuit, such that the gm output stage can be activated within a reduced time,
the switching point is a threshold voltage value at which a NMOS transistor is turned on, and
the desired voltage value includes a common mode of the output circuit.
10 . The method of claim 9 , further comprising:
configuring a series of multiplexers in the one or more serialization stages of the serialization circuit, wherein the last serialization stage is a multiplexer having a plurality of inputs, and
connecting, by the logic circuit, a plurality of bits input from the last serialization stage to a plurality of gm stages through a plurality of logic functions.
11 . The method of claim 10 , wherein the input of the last serialization stage is connected to the respective output stage with a relevant clock phase.
12 . The method of claim 11 , wherein the serialization circuit and the output circuit are connected by the logic circuit in a way that reduces data load of the last serialization stage and increases operation speed of the transmitter.
13 . The method of claim 9 , wherein each output stage is fed with digital data and output to a common resistor load to generate an analog symbol.
14 . The method of claim 9 , further comprising:
generating the data in the plurality of data branches, and
converting the data received in parallel from the plurality of data branches into a single sequence of data.
15 . The method of claim 9 , wherein the transmitter is one of a digital-to-analog converter (DAC) based transmitter, a non-return- to-zero (NRZ) transmitter, or other types of transmitters.
16 . The method of claim 9 , further comprising:
connecting the logic circuit to an external reference voltage; and adjusting the logic circuit to enable a current source to operate in saturation.