Image sensors with low noise readout

1 . Imaging circuitry comprising:

a plurality of image pixels coupled to a pixel output line;

a first data converter circuit having an input coupled to the pixel output line and configured to output a first set of bits;

an integrator having an input coupled to the first data converter circuit; and

a second data converter circuit having an input coupled to the integrator and configured to output a second set of bits.

2 . The imaging circuitry of claim 1 , wherein the first data converter circuit comprises:

a capacitive digital-to-analog converter (DAC) having a plurality of capacitors and a plurality of switches;

a comparator having a first input coupled to the capacitive DAC; and

a successive-approximation-register (SAR) control logic coupled to an output of the comparator and configured to output signals for controlling the plurality of switches of the capacitive DAC.

3 . The imaging circuitry of claim 2 , wherein the first data converter circuit further comprises:

an autozero switch coupled between the output of the comparator and a second input of the comparator; and

a shunt capacitor coupled to the second input of the comparator.

4 . The imaging circuitry of claim 2 , wherein each switch in the plurality of switches is configured to operate in:

a first mode during which the switch is configured to pass through an input voltage from the pixel output line;

a second mode during which the switch is configured to pass through a first reference voltage; and

a third mode during which the switch is configured to pass through a second reference voltage different than the first reference voltage.

5 . The imaging circuitry of claim 2 , wherein the first data converter circuit further comprises:

an offset capacitor coupled to the plurality of capacitors, wherein the offset capacitor is smaller than a smallest capacitor in the plurality of capacitors; and

an offset switch coupled in series with the offset capacitor, wherein the offset switch is configured to operate in:

a first mode during which the switch is configured to pass through a first reference voltage; and

a second mode during which the switch is configured to pass through a second reference voltage different than the first reference voltage.

6 . The imaging circuitry of claim 2 , wherein the first data converter circuit further comprises:

a skip logic having an input coupled to the integrator and configured to output a corresponding skip flag to the successive-approximation-register (SAR) control logic.

7 . The imaging circuitry of claim 2 , wherein the integrator comprises:

an amplifier having a first input coupled to the plurality of capacitors of the capacitive DAC; and

an integration capacitor coupled to an output of the amplifier.

8 . The imaging circuitry of claim 7 , wherein the integrator further comprises:

an autozero switch coupled between the output of the amplifier and a second input of the amplifier; and

a shunt capacitor coupled to the second input of the amplifier.

9 . The imaging circuitry of claim 7 , wherein the integrator further comprises:

a null switch configured to selectively pass through a reference voltage to the first input of the amplifier.

10 . The imaging circuitry of claim 7 , wherein the integrator further comprises:

an integration switch coupled between the output of the amplifier and the integration capacitor; and

a reset switch configured to selectively discharge the integration capacitor.

11 . The imaging circuitry of claim 1 , wherein the second data converter circuit comprises:

a comparator having a first input coupled to the integrator and a second input configured to receive a ramp voltage; and

a counter controlled by the comparator and configured to output the second set of bits.

12 . A method of operating imaging circuitry comprising:

with a first data converter, sampling a reset voltage;

with an integrator having an input coupled to the first data converter, generating a first integrated value during a first integration phase;

with a second data converter different than the first data converter, performing first conversion operations based on the first integrated value;

with the first data converter, sampling an image signal voltage and then performing second conversion operations to produce a coarse code; and

with the integrator, generating a second integrated value during a second integration phase.

13 . The method of claim 12 , further comprising:

with the second data converter, performing third conversion operations to produce a fine code; and

computing a final output by shifting the coarse code, scaling the fine code based on a calibrated value, and combining the shifted coarse code with the scaled fine code.

14 . The method of claim 12 , wherein the first data converter comprises a successive-approximation-register (SAR) analog-to-digital converter (ADC), and wherein the integrator comprises a transconductance amplifier coupled to an integration capacitor, the method further comprising:

after sampling the reset voltage, autozeroing a comparator of the SAR ADC; and

before the first integration phase, autozeroing the transconductance amplifier of the integrator.

15 . The method of claim 14 , further comprising:

after autozeroing the comparator of the SAR ADC, applying a reference voltage to the input of the integrator; and

after performing the second conversion operations, applying the reference voltage to the input of the integrator.

16 . The method of claim 14 , further comprising:

after the first conversion operations and before the second integration phase, discharging or resetting the integration capacitor.

17 . The method of claim 12 , further comprising:

determining, based on the sampled reset voltage and the sampled image signal voltage, whether to skip at least the sampling of the image signal voltage and the second conversion operations.

18 . The method of claim 12 , wherein the first and second integration phases each have a duration of greater than or equal to 100 nanoseconds for mitigating thermal and flicker noise.

19 . A method of operating imaging circuitry comprising:

during a vertical blanking period, performing calibration to obtain a calibrated value; and

during readout:

using a first data converter to output a coarse value;

using a second data converter to output a fine value; and

computing a final readout value based on the coarse value, the fine value, and the calibrated value.

20 . The method of claim 19 , further comprising:

with an integrator coupled between the first and second data converters, charging up an integration capacitor, wherein computing the final readout value comprises shifting the coarse value, computing a scaling factor based on the calibrated value, scaling the fine value by the scaling factor, and combining the shifted coarse value with the scaled fine value.