IP Library Granted Patent US 12696385
Granted Patent B2
US 12696385 · App. 18/639,407 · Granted Jul 28, 2026

Wiring board and manufacturing method therefor

Inventor: Tomoyuki Ishii (Tokyo, JP)
Assignee: TOPPAN HOLDINGS INC.
H05K1/0306H05K3/0017H05K3/4644H05K2201/0266H05K2201/0338H05K2201/09154H05K2203/0548H05K2203/1105
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Quick Facts
Patent No.
US 12696385
App. No.
18/639,407
Granted
Jul 28, 2026
Kind
B2
Abstract

A wiring board includes: a substrate; a first seed layer provided on the substrate; a first conductive layer provided on the first seed layer; a first insulating layer provided on the first conductive layer; a second seed layer provided on the first insulating layer; and a second conductive layer provided on the second seed layer. An area of the first insulating layer is smaller than an area of the first conductive layer. An area of the second conductive layer is smaller than the area of the first insulating layer. A region of the first insulating layer not overlapping the second conductive layer includes a first region surrounding the second conductive layer and a second region outside the first region. A surface roughness of the second region is larger than a surface roughness of the first region.

Claims (34)

1 . A wiring board, comprising:

a substrate having an insulating surface;

a first seed layer provided on the substrate;

a first conductive layer provided on the first seed layer;

a first insulating layer provided on the first conductive layer;

a second seed layer provided on the first insulating layer;

a second conductive layer provided on the second seed layer; and

a second insulating layer provided around the first seed layer, the first conductive layer, the first insulating layer, the second seed layer, and the second conductive layer, wherein

an area of the first insulating layer is smaller than an area of the first conductive layer,

an area of the second conductive layer is smaller than the area of the first insulating layer,

a region of the first insulating layer not overlapping the second conductive layer includes a first region surrounding the second conductive layer and a second region outside the first region, and

a surface roughness of the second region is larger than a surface roughness of the first region.

2 . The wiring board according to claim 1 , wherein

a thickness of the second region is smaller than a thickness of the first region.

3 . The wiring board according to claim 1 , wherein

a width of each of four corners of the second region is larger than a width of a linear portion of the second region.

4 . The wiring board according to claim 1 , wherein

a ratio of a surface roughness of the second region to a surface roughness of the first region is 1.2 or more and 10 or less.

5 . The wiring board according to claim 1 , wherein

a width of the second region is 1 μm or more and 10 μm or less.

6 . The wiring board according to claim 1 , wherein

a surface roughness of a lower surface of the first insulating layer is smaller than a surface roughness of the second region.

7 . The wiring board according to claim 1 , wherein

a side wall of the first insulating layer has a forward tapered shape.

8 . The wiring board according to claim 1 , wherein

the first conductive layer includes a side etching portion provided under an end of the first insulating layer.

9 . The wiring board according to claim 8 , wherein

a surface roughness of a region of the first conductive layer where the side etching portion is provided is larger than a surface roughness of a region other than the side etching portion.

10 . The wiring board according to claim 8 , wherein

a ratio of a width to a height of the side etching portion is 0.03 or more and 50 or less.

11 . The wiring board according to claim 8 , wherein

the second insulating layer includes one or more fillers provided in the side etching portion.

12 . The wiring board according to claim 11 , wherein

a size of the filler is ½ or more of a height of the side etching portion.