Three-dimensional static random-access memory and preparation method therefor

1 . A method for manufacturing a three-dimensional static random-access memory, comprising:

forming a first semiconductor structure, wherein the first semiconductor structure comprises a plurality of MOS transistors and a first insulating layer formed on the plurality of MOS transistors;

bonding a first material layer to the first insulating layer, and thinning the first material layer and processing a surface of the thinned first material layer to form a first substrate layer;

forming a second semiconductor structure on the first substrate layer, wherein the second semiconductor structure comprises a plurality of first MOS transistors on the first substrate layer and a second insulating layer on the plurality of first MOS transistors, and the plurality of first MOS transistors is formed at a first temperature;

bonding a second material layer to the second insulating layer, and thinning the second material layer and processing a surface of the thinned second material layer to form a second substrate layer;

forming a third semiconductor structure on the second substrate layer, wherein the third semiconductor structure comprises a plurality of second MOS transistors on the second substrate layer and a third insulating layer on the plurality of second MOS transistors, and the plurality of second MOS is formed at a second temperature;

forming a through-hole within the first insulating layer, the second semiconductor structure, and the third semiconductor structure;

depositing metal in the through-hole to form an interconnection layer which interconnects the first semiconductor structure, the second semiconductor structure and the third semiconductor structure;

wherein the first semiconductor structure comprises a first layer of metal contact located at an interface between the first insulating layer and the plurality of MOS transistors, the second semiconductor structure comprises a second layer of metal contact located at an interface between the second insulating layer and the plurality of first MOS transistors, the third semiconductor structure comprises a third layer of metal contact located at an interface between the third insulating layer and the plurality of second MOS transistors, and the interconnection layer extends from the first layer of metal contact via the second layer of metal contact to the third layer of metal contact;

wherein the plurality of MOS transistors serves as driving components in a first layer of a SRAM, the plurality of first MOS transistors serves as load components in a second layer of the SRAM, and the plurality of second MOS transistors severs as transmission components in a third layer of the SRAM.

2 . The method according to claim 1 , wherein

the plurality of MOS transistors, the plurality of first MOS transistors, and the plurality of second MOS transistors are CMOS transistors;

the first temperature and the second temperature are lower than a temperature at which the plurality of MOS transistors are formed;

each of the first material layer and the second material layer is a monocrystalline silicon wafer, a monocrystalline germanium wafer, or a silicon-on-insulator substrate.

3 . The method according to claim 1 , wherein:

the first material layer is bonded to the first insulating layer through silicon-to-silicon direct bonding, metal surface bonding, polymer bonding, or eutectic bonding, and

the second material layer is bonded to the second insulating layer through silicon-to-silicon direct bonding, metal surface bonding, polymer bonding, or eutectic bonding.

4 . The method according to claim 3 , wherein bonding the first material layer to the first insulating layer through the silicon-to-silicon direct bonding process comprises:

planarizing a surface of the first insulating layer;

rinsing the planarized surface of the first insulating layer, wherein a monolayer of water molecules is retained on the planarized surface of the first insulating layer after the rinsing;

oxidizing a surface of the first material layer to form an oxidation surface;

disposing the first material layer on the rinsed surface of the first insulating layer, wherein the oxidation surface is in contact with the rinsed surface of the first insulating layer;

bonding the oxidation surface to the rinsed surface of the first insulating layer in a face-to-face manner; and

annealing the first material layer and the first insulating layer after the bonding.

5 . The method according to claim 4 , wherein after oxidizing the surface of the first material layer and before disposing the first material layer on the rinsed surface of the first insulating layer, the method further comprises:

performing plasma activation on the oxidation surface and the rinsed surface of the first insulating layer.

6 . The method according to claim 4 , wherein bonding the oxidation surface to the rinsed surface of the first insulating layer in the face-to-face manner comprises:

pressing the oxidation surface of the first material layer against the rinsed surface of the first insulating layer under a mechanical pressure.

7 . The method according to claim 1 , wherein each of the first insulating layer, the second insulating layer, and the third insulating layer is made of SiO 2 , Si 3 N 4 or SiN, and has a thickness ranging from 300 nm to 3 μm.

8 . The method according to claim 1 , wherein the first temperature and the second temperature are greater than 0° C. and lower than 500° C.

9 . The method according to claim 1 , wherein manufacturing one of the plurality of first MOS transistors comprises:

forming an active region on the first substrate layer;

manufacturing a sacrificial gate in the active region;

doping the active region at two sides of the sacrificial gate to form source-or-drain extending regions; and

forming a spacer at a sidewall of the sacrificial gate, wherein the spacer covers at least a part of the source-or-drain extending regions;

doping the active region at a side of the source-or-drain extending regions away from the source-or-drain extending regions to form source-or-drain regions;

depositing an oxide dielectric layer on the sacrificial gate, the spacer, and the source-or-drain regions;

planarizing the oxide dielectric layer to expose a top of the sacrificial gate;

replacing the exposed sacrificial gate with a gate structure; and

forming a plurality of metal contacts for the one of the plurality of first MOS transistors.

10 . The method according to claim 9 , wherein doping the source-or-drain extending regions comprises;

doping the source-or-drain extending regions with impurities; or

forming fully siliconized metal at the source-or-drain extending regions.

11 . A three-dimensional static random-access memory, comprising:

a first semiconductor structure, wherein the first semiconductor structure comprises a plurality of MOS transistors and a first insulating layer that is formed on the plurality of MOS transistors;

a second semiconductor structure, wherein the second semiconductor structure comprises a plurality of first MOS transistors and a second insulating layer that is formed on the plurality of first MOS transistors;

a third semiconductor structure, wherein the third semiconductor structure comprises a plurality of second MOS transistors and a third insulating layer that is formed on the plurality of second MOS transistors; and

an interconnection layer extending vertically within the first insulating layer, the second semiconductor structure, and the third semiconductor structure, wherein the interconnection layer is configured to interconnect the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure;

wherein the plurality of first MOS transistors is formed on the first insulating layer, and a substrate of the plurality of first MOS transistors is bonded to a side of the first insulating layer away from the plurality of MOS transistors;

wherein the plurality of second MOS transistors is formed on the second insulating layer, and a substrate of the plurality of second MOS transistors is bonded to a side of the second insulating layer away from the plurality of first MOS transistors; and

wherein the first semiconductor structure comprises a first layer of metal contact located at an interface between the first insulating layer and the plurality of MOS transistors, the second semiconductor structure comprises a second layer of metal contact located at an interface between the second insulating layer and the plurality of first MOS transistors, the third semiconductor structure comprises a third layer of metal contact located at an interface between the third insulating layer and the plurality of second MOS transistors, and the interconnection layer extends from the first layer of metal contact via the second layer of metal contact to the third layer of metal contact;

wherein the plurality of MOS transistors serves as driving components in a first layer of a SRAM, the plurality of first MOS transistors serves as load components in a second layer of the SRAM, and the plurality of second MOS transistors severs as transmission components in a third layer of the SRAM.

12 . The three-dimensional static random-access memory according to claim 11 , wherein:

the plurality of MOS transistors, the plurality of first MOS transistors, and the plurality of second MOS transistors are CMOS transistors.

13 . The three-dimensional static random-access memory according to claim 11 , wherein:

each of the first insulating layer, the second insulating layer, and the third insulating layer is made of SiO 2 , Si 3 N 4 or SiN, and has a thickness ranging from 300 nm to 3 μm.

14 . The method according to claim 11 , wherein one of the plurality of first MOS transistors comprises: a gate structure; a spacer at two sides of the gate structure;

source-or-drain extending regions, wherein the source-or-drain extending regions are doped, and at least a part of the source-or-drain extending regions is located beneath the spacer;

source-or-drain regions, wherein the source- or drain regions are doped and located at a side of the source-or-drain extending regions away from the gate structure;

an oxide dielectric layer, covering the gate structure, the spacer, and the source-or-drain regions; and

a plurality of metal contacts on the oxide dielectric layer.