Support structure for multiple, alternating epitaxial silicon

1 . A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and storage nodes, comprising:

epitaxially forming multiple, alternating layers of silicon germanium (SiGe) material and single crystalline silicon (Si) material from a substrate to form a vertical stack;

forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack, the first vertical openings extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with first vertical sidewalls in the stack;

filling the plurality of first vertical openings with a first dielectric material;

forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls adjacent a first region of the epitaxially grown SiGe material and Si material;

selectively etching the epitaxially grown SiGe material and one or more of the epitaxially grown Si layers in the second horizontal direction to form a plurality of first horizontal openings extending a first distance (D 1 ) from the second vertical opening;

selectively etching the first dielectric in the first horizontal direction to form continuous horizontal openings for access lines;

conformally depositing a second dielectric material on exposed surfaces in the first horizontal openings to provide a support structure to remaining epitaxially grown Si layers;

depositing a third dielectric material to fill the continuous horizontal openings;

selectively etching the second dielectric material a second distance (D 2 ) from the second vertical opening; and

depositing a first conductive material on a gate dielectric material on exposed surfaces of the epitaxially formed Si material to form horizontally oriented access lines opposing channel regions of the Si material, wherein the gate dielectric material is formed by:

using atomic layer deposition to first deposit a layer of an oxide material on exposed surfaces of the epitaxially formed Si material; and

using thermal oxidation to densify the ALD deposited oxide material.

2 . The method of claim 1 , wherein selectively etching the epitaxially grown silicon germanium (SiGe) to form the plurality of first horizontal openings extending a first distance (D 1 ) from the second vertical opening comprises using a timed exhume process.

3 . The method of claim 1 , wherein selectively etching the epitaxially grown SiGe material and one or more of the epitaxially grown Si layers in the second horizontal direction to form a plurality of first horizontal openings extending a first distance (D 1 ) from the second vertical opening comprises thinning remaining epitaxially grown Si layers to provide a vertical height (h 1 ) separating the thinned remaining epitaxially grown Si layers in a range of approximately 500 to 900 angstroms (Å).

4 . The method of claim 1 , wherein selectively etching the epitaxially grown SiGe material and one or more of the epitaxially grown Si layers in the second horizontal direction to form a plurality of first horizontal openings extending a first distance (D 1 ) from the second vertical opening comprises thinning remaining epitaxially grown Si layers to provide a remaining, thinned thickness (t 1 ) from an original thickness (t 2 ) in a range of approximately 50 to 250 angstroms (Å).

5 . The method of claim 1 , further comprising conformally depositing the second dielectric material using a silicon nitride material to have a conformal thickness (t 3 ) in a range of approximately 20 to 80 angstroms (Å).

6 . The method of claim 1 , further comprising epitaxially growing the Si material to have an original thickness (t 2 ) in a range of approximately 50 to 600 angstroms (Å).

7 . The method of claim 1 , wherein depositing a first conductive material comprises depositing the first conductive material fully around every surface of the Si material, to form gate all around (GAA) gate structures, opposing channel regions to form horizontally oriented access devices.

8 . The method of claim 1 , wherein selectively etching the second dielectric material comprises removing the second dielectric material using a timed exhume process a second distance (DIST 2 ) in a range of approximately twenty-five (25) to seventy-five (75) nanometers (nm) from the second vertical opening.

9 . The method of claim 1 , further comprising selectively recessing a first conductive material and a gate dielectric material in the second direction, and in the continuous second horizontal openings, a second distance (DIST 3 ) in a range of twenty (20) to fifty (50) nanometers (nm) back from the second vertical opening.

10 . The method of claim 1 , further comprising selectively recessing the first conductive material and the gate dielectric material a second distance (DIST 3 ) around the Si material back into the first horizontal openings extending in the first horizontal direction using an atomic layer etching (ALE) process.

11 . The method of claim 1 , further comprising:

forming a third vertical opening adjacent a second region of the epitaxially grown silicon germanium (SiGe) material and single crystalline silicon (Si) material to expose third vertical sidewalls in the vertical stack;

selectively etching the epitaxially grown, single crystalline silicon (Si) material in the second horizontal direction, using remaining, un-etched second dielectric material as an etch stop, to form a plurality of second horizontal openings in the second region;

gas phase doping a dopant in a side surface of the epitaxially grown, single crystalline silicon (Si) material from the second horizontal openings to form second source/drain regions horizontally adjacent channel regions; and

depositing horizontally oriented capacitor cells having a bottom electrode formed in electrical contact with the second source/drain regions.

12 . The method of claim 1 , the method further comprising forming a plurality of patterned fourth vertical openings through the vertical stack adjacent first source/drain regions in which to deposit a second conductive material to form vertically oriented digit lines.

13 . The method of claim 12 , further comprising:

depositing a doped, n-type poly silicon (Si) material in the plurality of patterned fourth vertical openings through the vertical stack adjacent first source/drain regions to form the vertically oriented digit lines; and

annealing to diffuse n-type dopants from the n-type poly silicon (Si) material into the epitaxially grown Si material to form first source/drain regions in the horizontally oriented access devices adjacent channel regions.

14 . A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and storage nodes, comprising:

epitaxially forming multiple, alternating layers of silicon germanium (SiGe) and single crystalline silicon (Si) from a substrate to form a vertical stack;

forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack, the first vertical openings extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with first vertical sidewalls in the stack;

filling the plurality of first vertical openings with a first dielectric material;

forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls adjacent a first region of the epitaxially grown SiGe and Si;

selectively etching the epitaxially grown SiGe and one or more of the epitaxially grown Si in the second horizontal direction to form a plurality of first horizontal openings extending a first distance (D 1 ) from the second vertical opening;

conformally depositing a second dielectric material on exposed surfaces of the epitaxially grown Si to provide a support structure;

depositing a third dielectric material to fill the first horizontal openings;

selectively etching the second dielectric material a second distance (D 2 ) from the second vertical opening to form a first conductive material on a gate dielectric material opposing channel regions of the epitaxially formed Si;

forming a third vertical opening adjacent a second region of the epitaxially grown SiGe and single crystalline Si to expose third vertical sidewalls in the vertical stack;

selectively etching the epitaxially grown, single crystalline Si in the second horizontal direction to form a plurality of second horizontal openings in the second region in which to form storage nodes; and

forming a plurality of patterned fourth vertical openings through the vertical stack adjacent first source/drain regions in which to deposit a second conductive material to form vertically oriented digit lines, wherein the second conductive material is a ruthenium (Ru) composition.

15 . The method of claim 14 , further comprising:

gas phase doping a dopant in a side surface of the epitaxially grown, single crystalline Si material from the second horizontal openings to form second source/drain regions; and

depositing horizontally oriented capacitor cells having a bottom electrode formed in electrical contact with the second source/drain regions.

16 . The method of claim 14 , further comprising:

removing a portion of the first dielectric material filled in the plurality of first vertical openings, between the first horizontal openings, to form continuous horizontal openings extending in the first horizontal direction;

depositing the first conductive material in the continuous second horizontal openings to form horizontally oriented access lines opposing channel regions of the epitaxially grown Si.

17 . The method of claim 14 , further comprising:

depositing a poly silicon (poly-Si) material having a high concentration of an n-type (n+) dopant in the patterned fourth vertical openings as the second conductive material; and

annealing to out-diffuse the n-type (n+) dopant into the epitaxially grown, single crystalline Si to form the first source/drain regions.

18 . The method of claim 17 , further comprising depositing a tungsten (W) material on the poly-Si material in the patterned fourth vertical openings.

19 . The method of claim 17 , further comprising depositing a titanium/titanium nitride (TiN) conductive material on the poly-Si material, via the patterned fourth vertical openings, to form a titanium silicide as part of the vertically oriented digit lines.

20 . The method of claim 17 , further comprising depositing a highly phosphorus (P) doped (n+) poly-silicon germanium (SiGe) material as the poly-Si material having a high concentration of an n-type (n+) dopant in the patterned fourth vertical openings.

21 . A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and storage nodes, comprising:

epitaxially forming multiple, alternating layers of silicon germanium (SiGe) material and single crystalline silicon (Si) material from a substrate to form a vertical stack;

forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack, the first vertical openings extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with first vertical sidewalls in the stack;

filling the plurality of first vertical openings with a first dielectric material;

forming a second vertical opening through the vertical stack and extending predominantly in the first horizontal direction to expose second vertical sidewalls adjacent a first region of the epitaxially grown SiGe material and Si material;

selectively etching, using a timed exhume process, the epitaxially grown SiGe material and one or more of the epitaxially grown Si layers in the second horizontal direction to form a plurality of first horizontal openings extending a first distance (D 1 ) from the second vertical opening;

selectively etching the first dielectric in the first horizontal direction to form continuous horizontal openings for access lines;

conformally depositing a second dielectric material on exposed surfaces in the first horizontal openings to provide a support structure to remaining epitaxially grown Si layers;

depositing a third dielectric material to fill the continuous horizontal openings;

selectively etching the second dielectric material a second distance (D 2 ) from the second vertical opening; and

depositing a first conductive material on a gate dielectric material on exposed surfaces of the epitaxially formed Si material to form horizontally oriented access lines opposing channel regions of the Si material.