Semiconductor device including an insulating structure on a sidewall of a landing pad
A semiconductor device includes bit lines extending in a first direction on a substrate, a lower contact connected to the substrate between two adjacent ones of the bit lines, a landing pad on the lower contact, and an insulating structure surrounding a sidewall of the landing pad, the insulating structure including a first insulating pattern having a top surface at a lower level than a top surface of the landing pad, and a second insulating pattern on the top surface of the first insulating pattern.
1 . A semiconductor device, comprising:
bit lines extending in a first direction on a substrate;
a bit line capping pattern on one of two adjacent tones of the bit lines;
a lower contact connected to the substrate between two adjacent ones of the bit lines;
a landing pad on the lower contact; and
an insulating structure surrounding a sidewall of the landing pad, the insulating structure including:
a first insulating pattern having a top surface at a lower level than a top surface of the landing pad, and
a second insulating pattern on and contacting the top surface of the first insulating pattern,
wherein the top surface of the first insulating pattern has a concave shape toward the substrate,
wherein an edge portion of a top surface of the second insulating pattern is coplanar with the top surface of the landing pad,
wherein a central portion of the top surface of the second insulating pattern has a shape that is concave toward the substrate, and
wherein a lowest portion of the top surface of the first insulating pattern is at a lower level than an uppermost surface of the bit line capping pattern.
2 . The semiconductor device as claimed in claim 1 , wherein the first insulating pattern has a hydrogen concentration higher than that of the second insulating pattern.
3 . The semiconductor device as claimed in claim 1 , wherein the insulating structure further includes an interface layer between the sidewall of the landing pad and the first insulating pattern, the interface layer having an oxygen concentration lower than that of the first insulating pattern.
4 . The semiconductor device as claimed in claim 1 , wherein the first insulating pattern has a thickness greater than that of the second insulating pattern.
5 . The semiconductor device as claimed in claim 1 , further comprising:
an upper insulating layer on the top surface of the second insulating pattern,
wherein the upper insulating layer has a bottom end at a lower level than a center portion of the top surface of the landing pad.
6 . The semiconductor device as claimed in claim 1 , wherein the second insulating pattern has an oxygen concentration lower than that of the first insulating pattern.
7 . The semiconductor device as claimed in claim 1 , wherein a bottom end of the second insulating pattern is at a lower level than a top end of the bit line capping pattern.
8 . The semiconductor device as claimed in claim 1 , wherein a bottom end of the first insulating pattern is at a higher level than a bottom end of the bit line capping pattern.
9 . The semiconductor device as claimed in claim 1 , wherein the first insulating pattern has an air gap at a lower level than a bottom surface of the second insulating pattern.
10 . The semiconductor device as claimed in claim 1 ,
wherein the insulating structure further includes an interface layer between the sidewall of the landing pad and the first insulating pattern, and
wherein a top surface of the interface layer is substantially coplanar with the edge portion of the top surface of the second insulating pattern.
11 . The semiconductor device as claimed in claim 1 , wherein the first insulating pattern is hydrogen-enriched.
12 . A semiconductor device, comprising:
a substrate including active regions and a device isolation layer defining the active regions;
word lines intersecting the active regions, the word lines extending in a first direction;
bit line structures on the word lines, the bit line structures extending in a second direction perpendicular to the first direction;
a bit line capping pattern on one of two adjacent ones of the bit line structures;
spacer structures on sidewalls of the bit line structures;
a lower contact between the spacer structures, the lower contact being connected to a corresponding one of the active regions;
a landing pad on the lower contact and extending onto a top surface of a corresponding one of the bit line structures, the landing pad including a pad metal pattern and a barrier layer between the pad metal pattern and the lower contact;
an insulating structure surrounding a sidewall of the landing pad, the insulating structure including:
a first insulating pattern, the first insulating pattern having a top surface at a lower level than a top surface of the landing pad,
a second insulating pattern on the first insulating pattern, and
an interface layer between the first insulating pattern and the sidewall of the landing pad;
an upper electrode on the top surface of the landing pad; and
an upper insulating layer on the second insulating pattern,
wherein the top surface of the first insulating patter has a concave shape toward the substrate,
wherein an edge portion of a top surface of the second insulating pattern is coplanar with the top surface of the landing pad,
wherein a central portion of the top surface of the second insulating pattern has a shape that is concave toward the substrate, and
wherein a lowest portion of the top surface of the first insulating pattern is at a lower level than an uppermost surface of the bit line capping pattern.
13 . The semiconductor device as claimed in claim 12 , wherein a bottom end of the first insulating pattern vertically overlaps with a spacer structure of the spacer structures.
14 . The semiconductor device as claimed in claim 12 , wherein the first insulating pattern has a hydrogen concentration higher than that of the second insulating pattern.
15 . The semiconductor device as claimed in claim 12 , wherein the first insulating pattern has a thickness greater than that of the second insulating pattern.
16 . The semiconductor device as claimed in claim 12 , wherein the first insulating pattern has an air gap at a lower level than a bottom surface of the second insulating pattern.
17 . A semiconductor device, comprising:
a gate stack on a substrate, the gate stack including a gate electrode and a gate capping pattern on the gate electrode;
a gate spacer structure on a sidewall of the gate stack, the gate spacer structure including a gate spacer contacting a top surface of the gate capping pattern;
an interlayer insulating layer on a top surface of the gate stack and a top surface of the gate spacer structure;
peripheral circuit wiring lines on a top surface of the interlayer insulating layer;
a first wiring insulating pattern vertically overlapping with the gate electrode and filling a lower portion of a trench between the peripheral circuit wiring lines, a bottom end of the first wiring insulating pattern being at a lower level than the top surface of the interlayer insulating layer;
a second wiring insulating pattern extending from top surfaces of the peripheral circuit wiring lines into the trench; and
a wiring interface layer between an inner surface of the trench and the first wiring insulating pattern,
wherein the wiring interface layer contacts the first wiring insulating pattern, the gate capping pattern, and the gate spacer, and
wherein a top surface of the first wiring insulating pattern is located at a lower level than the top surfaces of the peripheral circuit wiring lines.
18 . The semiconductor device as claimed in claim 17 , wherein the bottom end of the first wiring insulating pattern is at a lower level than a top surface of the gate capping pattern.
19 . The semiconductor device as claimed in claim 17 , wherein the first wiring insulating pattern has a hydrogen concentration higher than that of the second wiring insulating pattern.