Semiconductor structure and method of manufacturing the same
A semiconductor structure includes a substrate, several buried word lines in the substrate, a dielectric material layer on the substrate, a semiconductor material layer on the dielectric material layer, and several contacts disposed on the substrate. The substrate includes several active regions and isolation structures that surround the active regions. The contacts are adjacent to the semiconductor material layer, and penetrate the semiconductor material layer, the dielectric material layer and parts of the substrate. The contacts are positioned in the respective active regions.
1 . A semiconductor structure, comprising:
a substrate that comprises active regions and isolation structures, and the isolation structures surround the active regions;
buried word lines disposed in the substrate;
a dielectric material layer formed on the substrate;
a semiconductor material layer formed on the dielectric material layer;
contacts adjacent to the semiconductor material layer, wherein the contacts penetrate the semiconductor material layer, the dielectric material layer and parts of the substrate, and the contacts are positioned in the respective active regions; and
a plurality of doping regions, wherein the doping regions are disposed between the semiconductor material layer and the respective contacts, so that the semiconductor material layer is separated from the contacts,
wherein top surfaces of the contacts are coplanar with top surfaces of the doping regions.
2 . The semiconductor structure as claimed in claim 1 , wherein the substrate includes an array region and a periphery region, and the semiconductor material layer extends over the array region and the periphery region, and
wherein the active regions and the contacts are positioned in the array region, and a portion of the semiconductor material layer that extends over the periphery region is a part of peripheral conductive wires.
3 . The semiconductor structure as claimed in claim 2 , wherein the semiconductor material layer includes:
a first semiconductor material portion formed in the array region; and
a second semiconductor material portion formed in the periphery region to form the part of peripheral conductive wires.
4 . The semiconductor structure as claimed in claim 1 , wherein top surfaces of the contacts are coplanar with top surface of the semiconductor material layer.
5 . The semiconductor structure as claimed in claim 1 , wherein the contacts and the semiconductor material layer are made of the same material.
6 . The semiconductor structure as claimed in claim 1 , further comprising:
a plurality of bit lines formed on the contacts and the semiconductor material layer, wherein top surfaces of the doping regions are in contact with bottom surfaces of the plurality of bit lines, and
wherein the buried word lines extend in a first direction, the plurality of bit lines extend in a second direction, and the first direction is different from the second direction.
7 . A method of manufacturing the semiconductor structure of claim 1 , comprising:
providing the substrate, wherein the substrate comprises the active regions and the isolation structures that surround the active regions, and the buried word lines disposed in the substrate;
forming the dielectric material layer on the substrate;
forming the semiconductor material layer on the dielectric material layer;
forming contact openings that penetrate the semiconductor material layer, the dielectric material layer and parts of the substrate, wherein the contact openings expose the substrate; and
forming the contacts in the contact openings, wherein the contacts are disposed adjacent to the semiconductor material layer, and the contacts are positioned in the respective active regions.
8 . The method of manufacturing the semiconductor structure as claimed in claim 7 , wherein the substrate includes an array region and a periphery region, and the semiconductor material layer extends over the array region and the periphery region, and
wherein the active regions and the contacts are positioned in the array region.
9 . The method of manufacturing the semiconductor structure as claimed in claim 7 , wherein top surfaces of the contacts are coplanar with a top surface of the semiconductor material layer.
10 . The method of manufacturing the semiconductor structure as claimed in claim 7 , wherein after the contact openings are formed to expose the substrate, the method further comprises:
forming a plurality of doping regions on sidewalls of the semiconductor material layer, wherein the plurality of doping regions are exposed in the contact openings.
11 . The method of manufacturing the semiconductor structure as claimed in claim 10 , wherein a pre-amorphization implantation is performed on the sidewalls of the semiconductor material layer that are exposed in the contact openings.
12 . The method of manufacturing the semiconductor structure as claimed in claim 10 , wherein after the contacts are formed, the doping regions are disposed between the semiconductor material layer and the respective contacts, so that the semiconductor material layer is separated from the contacts.
13 . The method of manufacturing the semiconductor structure as claimed in claim 10 , further comprising:
forming a plurality of bit lines on the contacts and the semiconductor material layer, wherein top surfaces of the doping regions are in contact with bottom surfaces of the plurality of bit lines, and
wherein the buried word lines extend in a first direction, the plurality of bit lines extend in a second direction, and the first direction is different from the second direction.
14 . The method of manufacturing the semiconductor structure as claimed in claim 10 , further comprising:
forming a first mask layer on the semiconductor material layer and forming a second mask layer on the first mask layer;
forming the contact openings to penetrate the second mask layer, the first mask layer, the semiconductor material layer, the dielectric material layer and the parts of the substrate, wherein the contact openings expose the substrate;
removing the second mask layer, wherein a top surface of the first mask layer is exposed after the second mask layer is removed;
depositing a conductive material layer over the substrate, wherein the conductive material layer covers the first mask layer and fully fills the contact openings;
removing portions of the conductive material layer over the top surface of the first mask layer, wherein a remaining portion of the conductive material layer in each of the contact openings is referred to as a conductive layer;
recessing the conductive layers in the contact openings to form the contacts, wherein sidewalls of the first mask layer are exposed after the conductive layers in the contact openings are recessed; and
removing the first mask layer.
15 . The semiconductor structure as claimed in claim 1 , wherein the semiconductor material layer includes a polysilicon layer.
16 . The semiconductor structure as claimed in claim 1 , wherein the doping regions include amorphous material.
17 . The semiconductor structure as claimed in claim 1 , wherein bottom surfaces of the doping regions are in contact with the dielectric material layer.
18 . The semiconductor structure as claimed in claim 17 , wherein the dielectric material layer includes:
a nitride layer formed on a top surface of the substrate; and
an oxide layer formed on the nitride layer,
wherein the bottom surfaces of the doping regions are in contact with a top surface of the oxide layer.