Semiconductor device and manufacturing method thereof
A semiconductor device, and a method of manufacturing a semiconductor device, includes first stack structures enclosing first channel structures and spaced apart from each other. The first channel structures are spaced apart from each other at a first distance in each of the first stack structures and the first stack structures are spaced apart from each other at a second distance.
1 . A semiconductor device comprising:
a first stack structure;
first channel structures passing through the first stack structure;
a gate insulating layer interposed between the first stack structure and each of the first channel structures;
a second stack structure disposed under the first stack structure;
second channel structures passing through the second stack structure; and
a memory layer interposed between the second stack structure and each of the second channel structures,
wherein each of the first channel structures includes a first portion and a second portion,
wherein the first portion is surrounded by the gate insulating layer,
wherein the second portion extends from the first portion toward a direction opposite to a corresponding second channel structure among the second channel structures to protrude above a top surface of the gate insulating layer,
wherein the first stack structure includes a select gate surrounding the first portion of each of the first channel structures and an insulating pattern disposed over the select gate, and
wherein a center of the first portion of each of the first channel structures at a level, where the select gate is located, is offset from a center of the corresponding second channel structure.
2 . The semiconductor device of claim 1 , further comprising an upper insulating layer between the first stack structure and the second stack structure,
wherein the first channel structures pass through the upper insulating layer to be coupled to the second channel structures, respectively.
3 . The semiconductor device of claim 1 , further comprising bit contact plugs disposed in the insulating pattern,
wherein the first channel structures are coupled to the bit contact plugs, respectively.
4 . The semiconductor device of claim 1 , further comprising a doped semiconductor layer disposed in a common source region under the second stack structure,
wherein the second channel structures contact the common source region.
5 . The semiconductor device of claim 1 , further comprising a core insulating layer disposed at a central region of each of the first channel structures,
wherein each of the first channel structures includes a capping pattern and a semiconductor layer, the capping pattern disposed over the core insulating layer, the semiconductor layer extending along a sidewall of the core insulating layer.
6 . The semiconductor device of claim 1 , wherein each of the first channel structures includes a pillar-shaped semiconductor layer.
7 . The semiconductor device of claim 1 , further comprising a core insulating layer disposed at central region of each of the second channel structures,
wherein each of the second channel structures includes a capping pattern and a semiconductor layer, the capping pattern disposed over the core insulating layer, the semiconductor layer extending along a sidewall of the core insulating layer and a bottom surface of the core insulating layer.
8 . The semiconductor device of claim 1 , wherein the second stack structure includes interlayer insulating layers and conductive patterns alternately stacked with each other.
9 . The semiconductor device of claim 1 , further comprising an insulating material filling each of a first separation region and a second separation region which are spaced apart from in a first direction,
wherein a portion of the first stack structure is defined by the first and second separation regions as a select stack structure.
10 . The semiconductor device of claim 9 ,
wherein the first channel structures include a first edge channel structure adjacent to the first separation region and a second edge channel structure adjacent to the second separation region,
wherein the second channel structures include a center channel structure adjacent to the first separation region, and
wherein a central region of the center channel structure is disposed closer to the first separation region than a central region of the first edge channel structure.
11 . The semiconductor device of claim 9 ,
wherein the first channel structures include a first edge channel structure adjacent to the first separation region and a second edge channel structure adjacent to the second separation region,
wherein the second edge channel structure of the first channel structures is coupled to a corresponding one of the second channel structures, and
wherein a central region of the second edge channel structure is disposed closer to the second separation region than a central region of the corresponding one of the second channel structures.
12 . The semiconductor device of claim 9 , wherein the first stack structure includes wavy sidewalls defined along the first separation region and the second separation region.
13 . The semiconductor device of claim 9 , wherein the first stack structure includes straight sidewalls defined along the first separation region and the second separation region.
14 . The semiconductor device of claim 9 , wherein the first stack structure includes a wavy sidewall defined along one of the first and second separation regions and a straight sidewall defined along the other of the first and second separation regions.
15 . The semiconductor device of claim 9 , wherein the first stack structure includes a wavy sidewall defined along the first separation region or the second separation region.
16 . The semiconductor device of claim 1 , wherein a direction of the offset is substantially the same for all channel structure pairs, each of the channel structure pairs including corresponding first and second channel structures.
17 . A semiconductor device comprising:
a first stack structure;
first channel structures passing through the first stack structure;
a gate insulating layer interposed between the first stack structure and each of the first channel structures;
a second stack structure disposed above the first stack structure;
second channel structures passing through the second stack structure; and
a memory layer interposed between the second stack structure and each of the second channel structures,
wherein each of the first channel structures includes a first portion surrounded by the gate insulating layer and a second portion extending from the first portion toward a corresponding second channel structure among the second channel structures,
wherein the second portion protrudes above a top surface of the gate insulating layer and is not surrounded by the corresponding second channel structure,
wherein the first stack structure includes a select gate surrounding the first portion of each of the first channel structures and an insulating pattern disposed over the select gate, and
wherein a center of the first portion of each of the first channel structures at a level, where the select gate is located, is offset from a center of the corresponding second channel structure.
18 . The semiconductor device of claim 17 , further comprising:
an upper insulating layer covering the second stack structure; and
bit contact plugs passing through to be coupled to the second channel structures, respectively.
19 . The semiconductor device of claim 17 , further comprising a doped semiconductor layer disposed in a common source region under the first stack structure,
wherein the first channel structures are coupled to the common source region.
20 . The semiconductor device of claim 17 , further comprising a core insulating layer disposed at a central region of each of the first channel structures,
wherein each of the first channel structures includes a capping pattern and a semiconductor layer, the capping pattern disposed over the core insulating layer, the semiconductor layer extending along a sidewall of the core insulating layer.
21 . The semiconductor device of claim 17 , wherein each of the first channel structures includes a pillar-shaped semiconductor layer.
22 . The semiconductor device of claim 17 , further comprising a core insulating layer disposed at a central region of each of the second channel structures,
wherein each of the second channel structures includes a capping pattern and a semiconductor layer, the capping pattern disposed over the core insulating layer, the semiconductor layer extending along a sidewall of the core insulating layer and a bottom surface of the core insulating layer.
23 . The semiconductor device of claim 17 , wherein the second stack structure includes interlayer insulating layers and conductive patterns alternately stacked with each other.
24 . The semiconductor device of claim 17 , wherein a direction of the offset is substantially the same for all channel structure pairs, each of the channel structure pairs including corresponding first and second channel structures.