Three-dimensional semiconductor memory device with high aspect ratio
A semiconductor memory device includes a stack structure and a slit structure. The stack structure includes insulation layers and conductive layers alternately stacked with the insulation layers. The slit structure is configured to divide the stack structure into memory blocks. A part of the slit structure configured to define one memory block has a dashed shape including a slit region and a bridge region.
1 . A semiconductor memory device comprising:
a plurality of memory blocks extending parallel to each other in a first direction, and
a plurality of first slit structures extending along the first direction, each of the plurality of first slit structures being positioned between adjacent memory blocks of the plurality of memory blocks to separate the plurality of memory blocks from one another,
wherein at least one of the plurality of memory blocks includes:
a first sub-memory block including a plurality of first conductive layers and a plurality of first insulation layers which are alternately stacked;
a second sub-memory block including a plurality of second conductive layers and a plurality of second insulation layers which are alternately stacked; and
a second slit structure positioned between the first sub-memory block and the second sub-memory block to divide the at least one memory block into the first sub-memory block and the second sub-memory block, the second slit structure including at least one bridge connecting the first sub-memory block and the second sub-memory block, and the second slit structure extending in parallel with the first direction and is disposed between adjacent first slit structures of the plurality of first slit structures,
wherein the plurality of first conductive lines layers of the first sub-memory block and the plurality of second conductive lines layers of the second sub-memory block are connected to each other at the at least one bridge.
2 . The semiconductor memory device of claim 1 , wherein the at least one bridge includes a plurality of third conductive layers and a plurality of third insulating layers which are alternately stacked.
3 . The semiconductor memory device of claim 2 , wherein the plurality of third conductive layers is connected between the plurality of first conductive layers and the plurality of second conductive layers, respectively.
4 . The semiconductor memory device of claim 1 , wherein at least one of the plurality of first conductive layers and the plurality of second conductive layers includes at least one source selection line, a plurality of word lines, and at least one drain selection line which are sequentially stacked.
5 . The semiconductor memory device of claim 4 , wherein the at least one source selection line, the plurality of word lines, and the at least one drain selection line are extended along the first direction.
6 . The semiconductor memory device of claim 1 , wherein each of the first sub-memory block and the second sub-memory block include:
a cell array region; and
a slimming region positioned at an edge of the cell array region and at least one portion of the slimming region including a plurality of contact regions for receiving electrical signals.
7 . The semiconductor memory device of claim 6 , wherein the at least one bridge is positioned between the cell array region of the first sub-memory block and the cell array region of the second sub-memory block, and between the slimming region of the first sub-memory block and the slimming region of the second sub-memory block.
8 . The semiconductor memory device of claim 1 , wherein each of the first and second sub-memory blocks comprises a first sidewall including a first stepped region and a second sidewall including a second stepped region different from the first stepped region that are parallel to the first direction, and
wherein the first sidewalls of the first and second sub-memory blocks contact different first slit structures of the plurality of first slit structures, respectively, and the second sidewalls of the first and second sub-memory blocks contact the second slit structure, respectively.
9 . The semiconductor memory device of claim 1 , wherein a depth of the first slit structure is equal to a depth of the second slit structure between the at least one bridge.
10 . The semiconductor memory device of claim 1 , wherein a length of the first slit structure in the first direction is equal to a length of the second slit structure in the first direction.
11 . The semiconductor memory device of claim 1 , wherein the plurality of first conductive lines layers of the first sub-memory block and the plurality of second conductive lines layers of the second sub-memory block are separated from each other by the second slit structure positioned outside of the at least one bridge.
12 . A semiconductor memory device comprising:
a plurality of memory blocks extending parallel to each other along a first direction; and
a plurality of first slit structures positioned individually between adjacent memory blocks of the plurality of memory blocks along the first direction to separate the plurality of memory blocks,
wherein at least one of the plurality of memory blocks includes:
a first sub-memory block and a second sub-memory block extending in parallel along the first direction; and
a second slit structure positioned between the first sub-memory block and the second sub-memory block, the second slit structure including at least one bridge connecting the first sub-memory block and the second sub-memory block, and
wherein sidewalls of the plurality of memory blocks facing the plurality of first slit structures includes high stepped regions, respectively, and sidewalls of the first and second sub-memory blocks facing the second slit structure include low stepped regions.
13 . The semiconductor memory device of claim 12 , wherein the first sub-memory block, the second sub-memory block and the at least one bridge include a plurality of conductive layers and a plurality of insulation layers which are alternately stacked, respectively.
14 . The semiconductor memory device of claim 13 , wherein the plurality of conductive layers of the first sub-memory block and the plurality of conductive layers of the second sub-memory block are connected to each other by the plurality of conductive layers of the at least one bridge.
15 . The semiconductor memory device of claim 12 , wherein each of the first sub-memory block and the second sub-memory block include:
a cell array region; and
a slimming region positioned to surround the cell array region.
16 . The semiconductor memory device of claim 15 , wherein portions of the slimming region parallel to the first direction correspond to the high stepped region and the low stepped regions, and portions of the slimming region include a plurality of contact regions for receiving electrical signals.