Semiconductor memory device having horizontally spaced selection structures and electronic system including the same

1 . A semiconductor device, comprising:

a stack structure extending in a first direction and including a plurality of gate electrodes vertically stacked on a substrate;

a plurality of selection structures disposed on the stack structure and horizontally spaced apart from each other in a second direction that intersects the first direction;

an upper isolation structure extending in the first direction on the stack structure between the plurality of selection structures; and

a plurality of vertical structures penetrating the stack structure and the plurality of selection structures,

wherein the plurality of vertical structures include a plurality of first vertical structures penetrating portions of the upper isolation structure and arranged along the first direction, wherein each of the plurality of selection structures includes a selection gate electrode and a horizontal dielectric pattern,

wherein, in each of the plurality of selection structures,

the horizontal dielectric pattern surrounds a top surface of the selection gate electrode, a bottom surface of the selection gate electrode, and a sidewall surface of the selection gate electrode,

the selection gate electrode includes a line part and an electrode part,

the line part extends in the first direction,

the electrode part that vertically protrudes from the line part and surrounds at least a portion of each of the plurality of first vertical structures, and

wherein the first direction and the second direction are parallel to a top surface of the substrate.

2 . The semiconductor device of claim 1 ,

wherein each of the plurality of vertical structures includes a lower vertical structure and an upper vertical structure,

the lower vertical structure penetrates the plurality of gate electrodes, and

the upper vertical structure penetrates the selection gate electrode of a corresponding selection structure among the plurality of selection structures,

wherein, in each of the plurality of vertical structures, the lower vertical structure includes a lower channel pattern, a data storage layer surrounding the lower channel pattern, and a lower conductive pad on the lower channel pattern, and

wherein, in each of the plurality of vertical structures, the upper vertical structure includes an upper channel pattern connected to the lower conductive pad, a selection gate dielectric pattern surrounding the upper channel pattern, and an upper conductive pad on the upper channel pattern.

3 . The semiconductor device of claim 2 , wherein

the horizontal dielectric pattern includes a first sidewall part and a second sidewall part,

the first sidewall part is between the electrode part of the corresponding selection structure and the upper vertical structure, and

the second sidewall part is connected to the first sidewall part, and

the second sidewall part is between the upper isolation structure and the selection gate electrode of the corresponding selection structure.

4 . The semiconductor device of claim 3 , wherein

the first sidewall part of the horizontal dielectric pattern is between the selection gate dielectric pattern of the upper vertical structure and the electrode part of the selection gate electrode of the corresponding selection structure.

5 . The semiconductor device of claim 2 , wherein

the horizontal dielectric pattern is between the upper isolation structure and the electrode part of the selection gate electrode of the corresponding selection structure, and

the horizontal dielectric pattern is between the upper isolation structure and the line part of the selection gate electrode of the corresponding selection structure.

6 . The semiconductor device of claim 2 , wherein

in the corresponding selection structure, a bottom surface of the electrode part of the selection gate electrode is vertically spaced apart from a top surface of the lower vertical structure of a corresponding one of the vertical structures.

7 . The semiconductor device of claim 2 , wherein the selection gate dielectric pattern is a single layer.

8 . The semiconductor device of claim 1 , wherein

in a corresponding selection structure among the plurality of selection structures,

the electrode part of the selection gate electrode includes a first part and a second part,

the first part is connected to the line part, and

the second part is in contact with the upper isolation structure.

9 . The semiconductor device of claim 1 , wherein,

in a corresponding selection structure among the plurality of selection structures,

the line part of the selection gate electrode surrounds a portion of a corresponding one of the plurality of first vertical structures.

10 . The semiconductor device of claim 1 , wherein

in a corresponding selection structure among the plurality of selection structures,

the electrode part completely surrounds a corresponding one of the plurality of first vertical structures.

11 . The semiconductor device of claim 1 , wherein

the plurality of vertical structures further include a plurality of second vertical structures spaced apart from the upper isolation structure, and

in a corresponding selection structure among the plurality of selection structures, the selection gate electrode further includes a subsidiary electrode part that vertically protrudes from the line part and completely surrounds a corresponding one of the plurality of second vertical structures.

12 . The semiconductor device of claim 1 , wherein

the plurality of vertical structures further include a plurality of second vertical structures spaced apart from the upper isolation structure, and

in a corresponding selection structure among the plurality of selection structures, the line part of each of the selection gate electrode completely surrounds a corresponding one of the plurality of second vertical structures.

13 . The semiconductor device of claim 1 , wherein

in a corresponding selection structure among the plurality of selection structures,

an uppermost surface of the electrode part of the selection gate electrode is at a level lower than a level of an uppermost surface of the upper isolation structure.

14 . The semiconductor device of claim 1 , wherein

in a corresponding selection structure among the plurality of selection structures,

the line part of the selection gate electrode includes a first line part and a second line part vertically spaced apart from each other, and

the electrode part of the selection gate electrode connects the first line part and the second line part to each other.

15 . The semiconductor device of claim 1 , wherein

in a corresponding selection structure among the plurality of selection structures,

a top surface of the electrode part is at a level higher than a level of a top surface of the line part, and

a bottom surface of the electrode part is at a level lower than a level of a bottom surface of the line part.

16 . The semiconductor device of claim 1 , wherein

the selection gate electrode in each of the plurality of selection structures provide a plurality of selection gate electrodes, and

the plurality of selection gate electrode are formed of a same metallic material as the plurality of gate electrodes of the stack structure.

17 . The semiconductor device of claim 1 , wherein

in a corresponding selection structure among the plurality of selection structures,

the selection gate electrode includes a first selection gate electrode and a second selection gate electrode spaced apart from each other across the upper isolation structure, and

a line part of the first selection gate electrode faces an electrode part of the second selection gate electrode.

18 . The semiconductor device of claim 1 , wherein

the plurality of vertical structures are in a first column, a second column, a third column, and a fourth column arranged along a second direction that intersects the first direction,

the plurality of vertical structures in the first column, the second column, the third column, and the fourth column penetrate a corresponding selection structure among the plurality of selection structures, and

among the plurality of vertical structures, the plurality of first vertical structures are in the first column and adjacent to the upper isolation structure.

19 . A semiconductor device, comprising:

a peripheral circuit structure including a plurality of peripheral circuits integrated on a semiconductor substrate;

a semiconductor layer on the peripheral circuit structure;

a stack structure extending in a first direction and including a plurality of gate electrodes vertically stacked on the semiconductor layer;

a plurality of lower vertical structures penetrating the stack structure;

a plurality of selection structures disposed on the stack structure and horizontally spaced apart from each other in a second direction that intersects the first direction;

an upper isolation structure extending in the first direction on the stack structure between the plurality of selection structures; and

a plurality of upper vertical structures penetrating the plurality of selection structures and connecting with the plurality of lower vertical structures,

wherein the plurality of upper vertical structures include a plurality of first upper vertical structures that penetrate portions of the upper isolation structure and are arranged along the first direction,

wherein each of the plurality of selection structures includes a selection gate electrode and a horizontal dielectric pattern, wherein, in each of the plurality of selection structures,

the horizontal dielectric pattern surrounds a top surface of the selection gate electrode, a bottom surface of the selection gate electrode, and sidewall surfaces of the selection gate electrode,

the horizontal dielectric pattern includes a first sidewall part and a second sidewall part,

the first sidewall part is between the upper isolation structure and an electrode part of the selection gate electrode, and

the second sidewall part is between the upper isolation structure and a line part of the selection gate electrode,

the line part extends in the first direction,

the electrode part vertically protrudes from the line part and surrounds at least a portion of each of the plurality of first upper vertical structures,

wherein the first direction and the second direction are parallel to a top surface of the semiconductor substrate.

20 . An electronic system, comprising:

a semiconductor device that includes a cell array and an input/output pad electrically connected to a peripheral circuit around the cell array; and

a controller electrically connected through the input/output pad to the semiconductor device, the controller configured to control the semiconductor device,

wherein the cell array includes,

a stack structure extending in a first direction and including a plurality of gate electrodes vertically stacked on a substrate,

a plurality of selection structures disposed on the stack structure and horizontally spaced apart from each other in a second direction that intersects the first direction,

an upper isolation structure extending in the first direction on the stack structure between the plurality of selection structures, and

a plurality of vertical structures penetrating the stack structure and the plurality of selection structures,

wherein the plurality of vertical structures include a plurality of first vertical structures penetrating portions of the upper isolation structure,

wherein each of the plurality of selection structures includes a selection gate electrode and a horizontal dielectric pattern, and

wherein, in each of the plurality of selection structures,

the horizontal dielectric pattern surrounds a top surface, a bottom surface, and a sidewall surface of the selection gate electrode,

the selection gate electrode includes a line part and an electrode part,

the line part extends in the first direction,

the electrode part vertically protrudes from the line part and surrounds at least a portion of each of the plurality of first vertical structures,

wherein the first direction and the second direction are parallel to a top surface of the substrate.