Backside MRAM with frontside devices
Semiconductor devices and methods of forming the same include a front-end-of-line (FEOL) layer that includes a first transistor device. A first back-end-of-line (BEOL) layer is on a front side of the FEOL layer and includes a first electrical connection to the first transistor device. A second BEOL layer is on a back side of the FEOL layer and includes a first BEOL device with a second electrical connection to the first transistor device.
1 . A semiconductor device, comprising:
a front-end-of-line (FEOL) layer that includes a first transistor device and a second transistor device that is formed at a different depth within the FEOL layer as compared to a first transistor depth of the first transistor device;
a first back-end-of-line (BEOL) layer on a front side of the FEOL layer that includes a first electrical connection to the first transistor device and further includes a BEOL device electrically connected to the second transistor device; and
a second BEOL layer on a back side of the FEOL layer that includes a first BEOL device with a second electrical connection to the first transistor device.
2 . The semiconductor device of claim 1 , wherein the first BEOL device includes a first programmable resistance device.
3 . The semiconductor device of claim 2 , wherein the first BEOL layer further includes a second programmable resistance device, connected to the first transistor device by the first electrical connection.
4 . The semiconductor device of claim 3 , wherein the first programmable resistance device and the second programmable resistance device are selected from the group consisting of a magnetic tunnel junction cell, a phase change memory cell, and a resistive random access memory cell.
5 . The semiconductor device of claim 1 , wherein the first transistor device has a first polarity and the second transistor device has a second polarity.
6 . The semiconductor device of claim 1 , wherein the second BEOL layer includes a backside power distribution network.
7 . The semiconductor device of claim 1 , wherein the first BEOL layer includes a wordline and a source line in electrical communication with the first transistor device and the second BEOL layer includes a bitline in electrical communication with the first BEOL device.
8 . A semiconductor device, comprising:
a front-end-of-line (FEOL) layer that includes a first transistor device and a second transistor device, wherein the first transistor device has a first polarity and the second transistor device has a second polarity;
a first back-end-of-line (BEOL) layer on a front side of the FEOL layer that includes a first electrical connection to the first transistor device and a second electrical connection to the second transistor device; and
a second BEOL layer on a back side of the FEOL layer that includes a first BEOL device with a third electrical connection to the second transistor device.
9 . The semiconductor device of claim 8 , wherein the first BEOL device includes a first programmable resistance device.
10 . The semiconductor device of claim 9 , wherein the first BEOL layer further includes a second programmable resistance device, connected to the first transistor device by the first electrical connection.
11 . The semiconductor device of claim 10 , wherein the first programmable resistance device and the second programmable resistance device are selected from the group consisting of a magnetic tunnel junction cell, a phase change memory cell, and a resistive random access memory cell.
12 . The semiconductor device of claim 8 , wherein the second transistor device is formed at a different depth within the FEOL layer as compared to a first transistor depth of the first transistor device.
13 . The semiconductor device of claim 8 , wherein the second BEOL layer includes a backside power distribution network.
14 . The semiconductor device of claim 8 , wherein the first BEOL layer includes a wordline, a source line, and a bitline in electrical communication with the first transistor device and a wordline and a source line in electrical communication with the second transistor device and wherein the second BEOL layer includes a bitline in electrical communication with the second transistor device.
15 . A semiconductor device, comprising:
a front-end-of-line (FEOL) layer that includes a first transistor device with a first polarity and a second transistor device with a second polarity, the second transistor device being formed at a different depth within the FEOL layer as compared to a first transistor depth of the first transistor device;
a first back-end-of-line (BEOL) layer on a front side of the FEOL layer that includes a first electrical connection to the first transistor device; and
a second BEOL layer on a back side of the FEOL layer that includes a first BEOL device with a second electrical connection to the first transistor device.
16 . The semiconductor device of claim 15 , wherein the first BEOL device includes a first programmable resistance device.
17 . The semiconductor device of claim 16 , wherein the first BEOL layer further includes a second programmable resistance device, connected to the first transistor device by the first electrical connection.
18 . The semiconductor device of claim 17 , wherein the first programmable resistance device and the second programmable resistance device are selected from the group consisting of a magnetic tunnel junction cell, a phase change memory cell, and a resistive random access memory cell.
19 . The semiconductor device of claim 15 , wherein the second BEOL layer includes a backside power distribution network.
20 . The semiconductor device of claim 15 , wherein the first BEOL layer includes a wordline and a source line in electrical communication with the first transistor device and the second BEOL layer includes a bitline in electrical communication with the first BEOL device.