Memory device including a semiconducting metal oxide FIN transistor and methods of forming the same
A semiconductor device includes a semiconducting metal oxide fin located over a lower-level dielectric material layer, a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin, an access-level dielectric material layer embedding the gate electrode and the semiconducting metal oxide fin, a memory cell embedded in a memory-level dielectric material layer and including a first electrode, a memory element, and a second electrode, and a bit line overlying the memory cell. The first electrode may be electrically connected to a drain region within the semiconducting metal oxide fin through a first electrically conductive path, and the second electrode is electrically connected to the bit line.
1 . A semiconductor device comprising:
at least one lower-level dielectric material layer overlying a semiconductor substrate and having a top surface that is located within a first horizontal plane;
a semiconducting metal oxide fin located over the at least one lower-level dielectric material layer and extending along a first horizontal direction and having a width along a second horizontal direction, wherein the semiconducting metal oxide fin comprises a channel region having a doping of a first conductivity type and in contact with a first horizontal surface segment of the top surface of the at least one lower-level dielectric material layer, and a source region having a doping of a second conductivity type that is an opposite of the first conductivity type and contacting the channel region at a first junction and in contact with a second horizontal surface segment of the top surface of the at least one lower-level dielectric material layer;
a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, wherein the first junction continuously extends from the top surface of the at least one lower-level dielectric material layer to an interface between a top surface of the semiconducting metal oxide fin and the gate dielectric layer;
a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin along the second horizontal direction;
a source line laterally extending along the second horizontal direction and electrically connected the source region through a source contact via structure; and
an auxiliary source line laterally extending along the second horizontal direction, laterally offset from the semiconducting metal oxide fin and from the gate electrode, contacting a top surface of the gate dielectric layer, and electrically connected to the source line through a source connection via structure.
2 . The semiconductor device of claim 1 , wherein:
the semiconducting metal oxide fin further comprises a drain region having a doping of the second conductivity type and contacting the channel region at a second junction and in contact with a third horizontal surface segment of the top surface of the at least one lower-level dielectric material layer; and
the second junction continuously extends from the top surface of the at least one lower-level dielectric material layer to the interface between the top surface of the semiconducting metal oxide fin and the gate dielectric layer.
3 . The semiconductor device of claim 1 , wherein the gate dielectric layer is in contact with a fourth horizontal surface segment of the top surface of the at least one lower-level dielectric material layer.
4 . The semiconductor device of claim 1 , further comprising an access-level dielectric material layer having formed therein the gate electrode and the semiconducting metal oxide fin.
5 . The semiconductor device of claim 4 , further comprising a memory cell formed within a memory-level dielectric material layer that is vertically offset from the access-level dielectric material layer and comprising a first electrode, a memory element, and a second electrode.
6 . The semiconductor device of claim 5 , further comprising a bit line overlying the memory cell, wherein:
the first electrode is electrically connected to the drain region through a first electrically conductive path; and
the second electrode is electrically connected to the bit line.
7 . The semiconductor device of claim 6 , wherein the first electrically conductive path comprises:
a drain contact via structure contacting the drain region within the semiconducting metal oxide fin and formed within the access-level dielectric material layer; and
a metal plate contacting a top surface of the drain contact via structure.
8 . The semiconductor device of claim 1 , further comprising field effect transistors located on a single crystalline semiconductor layer within the semiconductor substrate and comprising a respective single crystalline semiconductor channel.
9 . The semiconductor device of claim 8 , further comprising first metal interconnect structures formed within the at least one lower-level dielectric material layer and electrically connected to a respective node of the field effect transistors located on the single crystalline semiconductor layer, wherein at least one of the first metal interconnect structures is electrically connected to the bit line through a subset of second metal interconnect structures overlying the top surface of the at least one lower-level dielectric material layer.
10 . A memory array comprising:
at least one lower-level dielectric material layer overlying a semiconductor substrate and having a top surface that is located entirely within a first horizontal plane;
a two-dimensional array of fin field effect transistors including a respective semiconducting metal oxide fin and located over the top surface of at least one lower-level dielectric material layer, wherein the respective semiconducting metal oxide fin comprises a respective channel region having a doping of a first conductivity type and in contact with a respective first horizontal surface segment of the top surface of the at least one lower-level dielectric material layer, a respective source region having a doping of a second conductivity type that is an opposite of the first conductivity type and contacting the respective channel region at a respective first junction and in contact with a respective second horizontal surface segment of the top surface of the at least one lower-level dielectric material layer, and a respective drain region;
a gate dielectric layer located on a top surface and sidewalls of each of the semiconducting metal oxide fins in the two-dimensional array of fin field effect transistors, wherein each of the first junctions continuously extends from the top surface of the at least one lower-level dielectric material layer to an interface between a top surface of a respective one of the semiconducting metal oxide fins and the gate dielectric layer;
gate electrode strips overlying a respective row of the semiconducting metal oxide fins, wherein each of the fin field effect transistors comprises a portion of a respective one of the gate electrode strips as a gate electrode;
a two-dimensional array of memory cells that are vertically offset from the two-dimensional array of fin field effect transistors and comprising a respective first electrode that is electrically connected to the drain region of a respective one of the two-dimensional array of fin field effect transistors, a respective memory element, and a respective second electrode;
bit lines laterally extending along a first horizontal direction, laterally spaced apart along a second horizontal direction that is perpendicular to the first horizontal direction, and electrically connected to a set of memory cells within the two-dimensional array of memory cells;
source lines laterally extending along the second horizontal direction, laterally spaced apart along the first horizontal direction, and electrically connected to a set of source regions located within the respective row of the semiconducting metal oxide fins through a respective row of source contact via structures; and
auxiliary source lines laterally extending along the second horizontal direction, arranged along the first horizontal direction such that rows of the semiconducting metal oxide fins and the auxiliary source lines alternate along the first horizontal direction in a plan view, contacting a respective segment of a top surface of the gate dielectric layer, and electrically connected to a respective one of the source lines through a respective row of source connection via structures.
11 . The memory device of claim 10 , wherein:
the respective semiconducting metal oxide fin further comprises a respective drain region having a doping of the second conductivity type and contacting the respective channel region at a respective second junction and in contact with a respective third horizontal surface segment of the top surface of the at least one lower-level dielectric material layer; and
each of the second junctions continuously extends from the top surface of the at least one lower-level dielectric material layer to the interface between the top surface of the respective one of the semiconducting metal oxide fins and the gate dielectric layer.
12 . The memory device of claim 11 , wherein the gate dielectric layer contacts a fourth horizontal surface segment of the top surface of the at least one lower-level dielectric material layer.
13 . The memory array of claim 10 , wherein the gate electrode strips overlie the respective row of the semiconducting metal oxide fins, are laterally spaced apart along the first horizontal direction among one another, and laterally extend along the second horizontal direction.
14 . The memory array of claim 13 , further comprising field effect transistors located on a single crystalline semiconductor layer located within the semiconductor substrate and comprising a respective single crystalline semiconductor channel, wherein each of the bit lines and the gate electrode strips is electrically connected to a respective one of the field effect transistors located on the single crystalline semiconductor layer through a respective subset of metal interconnect structures formed within the at least one lower-level dielectric material layer.
15 . A semiconductor device comprising:
at least one lower-level dielectric material layer overlying a semiconductor substrate and having a top surface that is located entirely within a first horizontal plane;
a plurality of semiconducting metal oxide fins located over the top surface of the at least one lower-level dielectric material layer and comprising a respective channel region having a doping of a first conductivity type and in contact with a respective first horizontal surface segment of the top surface of the at least one lower-level dielectric material layer, and a respective source region laterally offset from the respective channel region along a first horizontal direction, having a doping of a second conductivity type that is an opposite of the first conductivity type, and contacting the respective channel region at a respective first junction and in contact with a respective second horizontal surface segment of the top surface of the at least one lower-level dielectric material layer, and a respective drain region having a doping of the second conductivity type and contacting the respective channel region at a respective second junction and in contact with a respective third horizontal surface segment of the top surface of the at least one lower-level dielectric material layer;
a gate dielectric layer located on a top surface and sidewalls of the semiconducting metal oxide fin, wherein the first junction continuously extends from the top surface of the at least one lower-level dielectric material layer to an interface between a top surface of the semiconducting metal oxide fin and the gate dielectric layer;
a gate electrode located on the gate dielectric layer and straddling the semiconducting metal oxide fin along a second horizontal direction that is perpendicular to the first horizontal direction;
an access-level dielectric material layer having formed therein the gate electrode and the semiconducting metal oxide fin;
a memory cell formed within a memory-level dielectric material layer that is vertically offset from the access-level dielectric material layer; and
a drain contact via structure contacting top surfaces of the drain regions of the plurality of semiconducting metal oxide fins and top surfaces of portions of the access-level dielectric material layer located between neighboring pairs among the drain regions of the plurality of semiconducting metal oxide fins and providing an electrically conductive path between the memory cell and the drain regions of the plurality of semiconducting metal oxide fins.
16 . The semiconductor structure of claim 15 , wherein the gate dielectric layer contacts a fourth horizontal surface segment of the top surface of the at least one lower-level dielectric material layer.
17 . The semiconductor device of claim 15 , wherein:
the memory cell comprises a first electrode, a memory element, and a second electrode;
the first electrode is electrically connected to the drain region within the semiconducting metal oxide fin through a first electrically conductive path; and
the second electrode is electrically connected to a bit line that overlies the memory cell.
18 . The semiconductor device of claim 17 , further comprising first metal interconnect structures formed within the at least one lower-level dielectric material layer and electrically connected to a respective node of the field effect transistors located on the single crystalline semiconductor layer, wherein at least one of the first metal interconnect structures is electrically connected to the bit line through a subset of second metal interconnect structures overlying the top surface of the at least one lower-level dielectric material layer.
19 . The semiconductor device of claim 17 , wherein the first electrically conductive path comprises:
a drain contact via structure contacting the drain region within the semiconducting metal oxide fin and formed within the access-level dielectric material layer; and
a metal plate contacting a top surface of the drain contact via structure.
20 . The semiconductor device of claim 15 , further comprising:
a source line laterally extending along the second horizontal direction;
a source contact via structure contacting the source regions of the plurality of semiconducting metal oxide fins and the source line;
an auxiliary source line laterally extending along the second horizontal direction, laterally offset from the semiconducting metal oxide fin and from the gate electrode, contacting a top surface of the gate dielectric layer; and
a source connection via structure contacting the source line and the auxiliary source line.