IP Library Granted Patent US 12696468
Granted Patent B2
US 12696468 · App. 17/830,266 · Granted Jul 28, 2026

Semiconductor device with reverse-tapered structure and manufacturing method thereof

Inventors: Chien-Te Tu (Hsinchu, TW); Chee-Wee Liu (Taipei, TW)
Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.; NATIONAL TAIWAN UNIVERSITY
H10D30/014H10D30/031H10D30/43H10D30/6735H10D30/6757H10D62/121H10P14/3411H10P14/3462H10P50/242
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Quick Facts
Patent No.
US 12696468
App. No.
17/830,266
Granted
Jul 28, 2026
Kind
B2
Abstract

A method includes forming a semiconductor structure on a substrate; performing a first etching process on the semiconductor structure to form a fin structure upwardly extending above the substrate; performing a second etching process to trim the fin structure to have a reverse-trapezoidal cross-sectional profile; forming source/drain regions on opposite regions of the fin structure; forming a gate structure between the source/drain regions.

Claims (35)

1 . A method, comprising:

forming a semiconductor structure on a substrate;

performing a first etching process on the semiconductor structure under a first pressure to form a fin structure upwardly extending above the substrate;

performing a second etching process using a gas mixture comprising a bromine-containing gas and under a second pressure higher than the first pressure to trim the fin structure to have a reverse-trapezoidal cross-sectional profile, wherein the second pressure is in a range from about 8 to 12 Torr;

forming source/drain regions on opposite regions of the fin structure; and

forming a gate structure between the source/drain regions.

2 . The method of claim 1 , wherein the first etching process does not use the bromine-containing gas.

3 . The method of claim 1 , further comprising:

forming a shallow trench isolation structure around a lower portion of the fin structure after performing the first etching process and prior to performing the second etching process.

4 . The method of claim 1 , wherein forming the semiconductor structure on the substrate comprises alternately depositing sacrificial materials and channel materials to form a multi-layer stack on the substrate, and the fin structure comprises alternating sacrificial layers and channel layers, the sacrificial layers comprise remaining portions of the sacrificial materials and the channel layers comprise remaining portions of the channel materials.

5 . The method of claim 4 , wherein a first one of the sacrificial layers in a lower position has a higher germanium atomic concentration than a second one of the sacrificial layers in a higher position.

6 . The method of claim 5 , wherein the first one of the sacrificial layers has a germanium atomic concentration in a range from about 40 to 100 atomic percent, and the second one of the sacrificial layers has a germanium atomic concentration in a range from about 5 to 40 atomic percent.

7 . The method of claim 5 , wherein the germanium atomic concentration of the first one of the sacrificial layers decreases as a distance from the substrate increases.

8 . The method of claim 4 , wherein a first one of the sacrificial layers in a lower position has a thicker thickness than a second one of the sacrificial layers in a higher position.

9 . The method of claim 1 , wherein the second etching process has an etching rate increasing in a direction from an upper portion to a lower portion of the fin structure.

10 . The method of claim 1 , wherein the first pressure is in a range from about 3 to less than 8 Torr.

11 . A method, comprising:

alternately depositing first and second semiconductor layers on a substrate, a first one of the first semiconductor layers in a lower position having a higher germanium atomic concentration than a second one of the first semiconductor layers in a higher position;

performing a first etching process on the first and second semiconductor layers to form a fin structure on the substrate under a first pressure, the fin structure having alternating first and second nanostructures, the first nanostructures comprising remaining portions of the first semiconductor layers, and the second nanostructures comprising remaining portions of the second semiconductor layers;

performing, using a bromine-containing gas, a second etching process on the fin structure under a second pressure higher than the first pressure, wherein the second pressure is in a range from about 8 to 12 Torr;

forming epitaxial structures on either side of the fin structure;

removing the first nanostructures of the fin structure such that the second nanostructures of the fin structure are suspended over the substrate; and

forming a gate structure to surround each of the suspended second nanostructures.

12 . The method of claim 11 , wherein the first and second etching processes both are reactive ion etch processes.

13 . The method of claim 12 , wherein the first one of the first semiconductor layers has a germanium atomic concentration in a range from about 40 to 100 atomic percent, and the second one of the first semiconductor layers has a germanium atomic concentration in a range from about 5 to 40 atomic percent.

14 . The method of claim 11 , wherein the bromine-containing gas comprises HBr gas.

15 . The method of claim 11 , wherein the first etching process is performing by using an etching gas without the bromine-containing gas.

16 . The method of claim 11 , wherein after performing the second etching process, a lower portion of the fin structure has a smaller lateral dimension than an upper portion of the fin structure.

17 . A method, comprising:

forming a plurality of channel layers over a substrate, wherein the channel layers extends in a first direction, and the channel layers are arranged in a second direction substantially perpendicular to a top surface of the substrate;

forming source/drain regions over the substrate, the channel layers being disposed between the source/drain regions, wherein when viewed in a cross section taken along a third direction perpendicular to the first direction, a first one of the channel layers has a lateral dimension smaller than a lateral dimension of a second one of the channel layers; and

forming a gate structure extending along the third direction and surrounding each of the first and second ones of the channel layers.

18 . The method of claim 17 , wherein the first one of the channel layers has a smaller thickness than the second one of the channel layers.

19 . The method of claim 17 , wherein the first one of the channel layers is in a position lower than the second one of the channel layers.

20 . The method of claim 17 , wherein the channel layers each have a slant side surface.