Method for manufacturing high-electron-mobility transistor
A method for manufacturing a high-electron-mobility transistor includes the following steps: providing a semiconductor substrate, wherein the semiconductor substrate includes a channel layer and a barrier layer on the channel layer; forming a protective layer on the semiconductor substrate at a position corresponding to a gate opening; forming an overlay layer on the semiconductor substrate in an area around the protective layer, and removing the protective layer to form the gate opening; and forming a p-type layer in and at the gate opening and on the overlay layer.
1 . A method for manufacturing a high-electron-mobility transistor, comprising the steps of:
(a) providing a semiconductor substrate, wherein the semiconductor substrate comprises a channel layer and a barrier layer on the channel layer;
(b) forming a protective layer on the semiconductor substrate at a position corresponding to a gate opening;
(c) forming an overlay layer on the semiconductor substrate in an area around the protective layer, and removing the protective layer to form the gate opening;
(d) forming a p-type layer in and at the gate opening and on the overlay layer;
(e) forming and patterning a first dielectric layer on the overlay layer such that the first dielectric layer exposes the overlay layer at positions corresponding respectively to a source opening and a drain opening, and performing a platform separation process;
(f) performing an etching process at the positions corresponding respectively to the source opening and the drain opening in order to form the source opening and the drain opening; and
(g) forming and patterning an ohmic contact metal layer in and at the source opening and the drain opening, and establishing ohmic contact,
wherein said establishing ohmic contact is by forming an n-type gallium nitride layer on a bottom side of the source opening and a bottom side of the drain opening, with a carrier concentration higher than 10 19 ns*cm 3 , or by molecular beam epitaxy (MBE) with a carrier concentration higher than 10 20 ns*cm −3 .
2 . The method of claim 1 , further comprising the steps of:
(h) forming and patterning a second dielectric layer such that the second dielectric layer covers the first dielectric layer partially;
(i) forming and patterning a first metal layer such that the first metal layer covers areas corresponding respectively to the source opening, the gate opening, and the drain opening, covers the first dielectric layer partially, and covers the second dielectric layer partially; and
(j) forming and patterning a second metal layer such that the second metal layer covers areas corresponding respectively to the source opening and the drain opening and covers the first metal layer partially.
3 . The method of claim 2 , wherein the second dielectric layer is formed and patterned by plasma-enhanced chemical vapor deposition (PECVD).
4 . The method of claim 2 , wherein the second dielectric layer has a thickness less than or equal to 500 nm.
5 . The method of claim 1 , further comprising: patterning the p-type layer after completion of the step (d), such that the p-type layer is confined in and at the gate opening.
6 . The method of claim 1 , wherein the protective layer comprises silicon nitride as an ingredient, and the protective layer has a thickness greater than a thickness of the overlay layer.
7 . The method of claim 6 , wherein the thickness of the protective layer is 20 to 75 nm.
8 . The method of claim 1 , wherein the overlay layer has a thickness of 15 to 50 nm, and the barrier layer has a thickness of 12 to 25 nm.
9 . The method of claim 1 , wherein the overlay layer and the barrier layer are of a same material.
10 . The method of claim 1 , wherein the protective layer is formed by low-pressure chemical vapor deposition (LPCVD).
11 . The method of claim 1 , further comprising the step, to be performed before the protective layer is formed, of:
forming an in-situ dielectric layer on the barrier layer.
12 . The method of claim 11 , wherein the in-situ dielectric layer has a thickness of 20 to 50 nm.
13 . The method of claim 1 , wherein the p-type layer has a width of 2.5 to 3 μm.
14 . The method of claim 1 , wherein the first dielectric layer covers the p-type layer partially.
15 . The method of claim 1 , wherein the first dielectric layer is formed and patterned by low-pressure chemical vapor deposition (LPCVD).
16 . The method of claim 1 , wherein each of the source opening and the drain opening is a groove exposing the channel layer partially.
17 . The method of claim 16 , wherein each of the grooves has at least one lateral side and a bottom side, and the lateral side and the bottom side of each said groove form an angle of 30 to 90 degrees.