IP Library › Granted Patent US 12696476
Granted Patent B2
US 12696476 · App. 17/982,634 · Granted Jul 28, 2026

Semiconductor device and method for fabricating the same

Inventors: Hong Sik Shin (Seoul, KR); Jeong Yeon Seo (Seoul, KR); Sung Woo Kang (Suwon-si, KR); Dong Kwon Kim (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H10D30/6219H10D30/503H10D30/506H10D30/6211H10D62/121H10D84/0149H10D84/0158H10D84/832H10D84/834H10D88/00
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Quick Facts
Patent No.
US 12696476
App. No.
17/982,634
Granted
Jul 28, 2026
Kind
B2
Abstract

The semiconductor device including an active pattern on a substrate and extending in a first direction, a gate structure on the active pattern, including a gate electrode extending in a second direction different from the first direction, a source/drain pattern on at least one side of the gate structure, and a source/drain contact on the source/drain pattern and connected to the source/drain pattern, wherein with respect to an upper surface of the active pattern, a height of an upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact, and the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact, may be provided.

Claims (69)

1 . A semiconductor device comprising:

an active pattern on a substrate and extending in a first direction;

a gate structure on the active pattern, the gate structure comprising a gate electrode, the gate electrode extending in a second direction different from the first direction;

a source/drain pattern on at least one side of the gate structure; and

a source/drain contact on the source/drain pattern and connected to the source/drain pattern,

wherein with respect to an upper surface of the active pattern, a height of an upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact, and

the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact.

2 . The semiconductor device of claim 1 , wherein

the gate electrode comprises a line portion extending in the second direction and a protruding portion protruding from the line portion of the gate electrode, and

the protruding portion of the gate electrode comprises the upper surface of the gate electrode.

3 . The semiconductor device of claim 1 , wherein the lower source/drain contact comprises a lower source/drain filling layer and a lower source/drain barrier layer extending along a sidewall of the lower source/drain filling layer.

4 . The semiconductor device of claim 3 , wherein the lower source/drain barrier layer extends along a boundary between the lower source/drain filling layer and the source/drain pattern.

5 . The semiconductor device of claim 3 , wherein with respect to the upper surface of the active pattern, an upper surface of the lower source/drain filling layer is higher than an upper surface of the lower source/drain barrier layer.

6 . The semiconductor device of claim 5 , wherein

the lower source/drain filling layer comprises a protruding portion protruding from the upper surface of the lower source/drain barrier layer, and

a width in the first direction of the protruding portion of the lower source/drain filling layer decreases as the protruding portion becomes farther from the source/drain pattern in a third direction perpendicular to the substrate.

7 . The semiconductor device of claim 3 , wherein the upper source/drain contact has a single material layer structure.

8 . The semiconductor device of claim 1 , further comprising:

a contact insulating liner extending along a sidewall of the lower source/drain contact and in contact with the lower source/drain contact.

9 . The semiconductor device of claim 1 , further comprising:

a contact isolation structure on the substrate,

wherein the lower source/drain contact comprises a first sidewall extending in the first direction and a second sidewall extending in the second direction,

the contact isolation structure faces the first sidewall of the lower source/drain contact, and

with respect to an upper surface of the substrate, a height of an upper surface of the contact isolation structure is same as a height of the upper surface of the source/drain contact.

10 . The semiconductor device of claim 1 , further comprising:

a wiring line on the source/drain contact and extending in the first direction,

wherein the wiring line is in contact with the source/drain contact.

11 . A semiconductor device comprising:

an active pattern on a substrate and extending in a first direction;

a gate structure on the active pattern, the gate structure comprising a gate spacer and a gate electrode, the gate electrode extending in a second direction different from the first direction;

a source/drain pattern on at least one side of the gate structure;

a source/drain contact on the source/drain pattern and connected to the source/drain pattern;

a first wiring line on the source/drain contact, the first wiring line being in contact with the source/drain contact and extending in the first direction; and

a wiring structure on the first wiring line and connected to the first wiring line, the wiring structure comprising a via and a second wiring line,

wherein the source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact,

the gate electrode comprises a line portion extending in the second direction and a protruding portion protruding from the line portion of the gate electrode, and

the protruding portion of the gate electrode comprises an upper surface of the gate electrode.

12 . The semiconductor device of claim 11 , wherein with respect to an upper surface of the active pattern, a height of the upper surface of the gate electrode is same as a height of an upper surface of the source/drain contact and a height of an upper surface of the gate spacer.

13 . The semiconductor device of claim 11 , wherein

the lower source/drain contact comprises a lower source/drain filling layer and a lower source/drain barrier layer extending along a sidewall of the lower source/drain filling layer, and

with respect to an upper surface of the active pattern, an upper surface of the lower source/drain filling layer is higher than an upper surface of the lower source/drain barrier layer.

14 . The semiconductor device of claim 11 , further comprising:

a source/drain etch stop layer extending along a sidewall of the gate structure; and

a contact insulating liner extending along a sidewall of the lower source/drain contact, and in contact with the lower source/drain contact.

15 . The semiconductor device of claim 11 , further comprising:

a contact isolation structure on the substrate,

wherein the lower source/drain contact comprises a first sidewall extending in the first direction and a second sidewall extending in the second direction, and

the contact isolation structure faces the first sidewall of the lower source/drain contact, and is in contact with the gate spacer.

16 . A semiconductor device comprising:

a first active pattern on a substrate and extending in a first direction;

a second active pattern on the substrate and extending in the first direction, the second active pattern spaced apart from the first active pattern in a second direction;

a gate electrode extending in the second direction, the gate electrode being on the first active pattern and the second active pattern;

a first source/drain pattern on the first active pattern;

a second source/drain pattern on the second active pattern;

a first source/drain contact on the first source/drain pattern and connected to the first source/drain pattern;

a second source/drain contact on the second source/drain pattern and connected to the second source/drain pattern;

a contact isolation structure between the first source/drain contact and the second source/drain contact; and

a wiring line on the first source/drain contact, the wiring line extending in the first direction and in contact with the first source/drain contact,

wherein an upper surface of the gate electrode is coplanar with an upper surface of the first source/drain contact and an upper surface of the second source/drain contact, and

each of the first source/drain contact and the second source/drain contact comprises a lower source/drain contact and an upper source/drain contact on the lower source/drain contact.

17 . The semiconductor device of claim 16 , wherein

the lower source/drain contact comprises a lower source/drain filling layer and a lower source/drain barrier layer extending along a sidewall of the lower source/drain filling layer, and

with respect to an upper surface of the first active pattern, an upper surface of the lower source/drain filling layer is higher than an upper surface of the lower source/drain barrier layer.

18 . The semiconductor device of claim 16 , wherein

the gate electrode comprises a line portion extending in the second direction and a protruding portion protruding from the line portion of the gate electrode, and

the protruding portion of the gate electrode comprises the upper surface of the gate electrode.

19 . The semiconductor device of claim 16 , wherein an upper surface of the contact isolation structure is coplanar with the upper surface of the first source/drain contact and the upper surface of the second source/drain contact.

20 . The semiconductor device of claim 16 , further comprising:

a contact insulating liner extending along a sidewall of the lower source/drain contact and in contact with the lower source/drain contact.