IP Library Granted Patent US 12696477
Granted Patent B2
US 12696477 · App. 18/607,547 · Granted Jul 28, 2026

Vertical transistor and method for fabricating the same

Inventor: Young Gwang Yoon (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H10D30/63H10D99/00H10D62/80
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Quick Facts
Patent No.
US 12696477
App. No.
18/607,547
Granted
Jul 28, 2026
Kind
B2
Abstract

Various embodiments of the present invention disclosure are directed to a vertical transistor having different doping profiles in its upper channel layer and lower channel layer for reducing leakage current while enhancing contact resistance and a method for manufacturing the vertical transistor. According to an embodiment of the present invention disclosure, a semiconductor device comprises a lower contact, a vertical channel layer on the lower contact, the vertical channel layer including a metal component and an oxygen component, and an upper contact on the vertical channel layer. The vertical channel layer has a gradual doping profile in which a doping concentration of the metal component is lowest in an intermediate region and gradually increases from the intermediate region to the upper contact.

Claims (17)

1 . A method for manufacturing a vertical transistor, the method comprising:

forming a lower contact material on a substrate;

forming a lower channel material including a metal component and an oxygen component on the lower contact material;

forming a channel material including a metal component and an oxygen component on the lower channel material; and

performing a treatment on the channel material to separate the channel material into an intermediate channel material and an upper channel material on the intermediate channel material forming a lower contact, a lower channel layer, an intermediate channel layer, and an upper channel layer by etching the lower contact material, the lower channel material, the intermediate channel material, and the upper channel material after performing the treatment;

forming an upper insertion layer on the upper channel layer; and

forming an upper barrier layer on the upper insertion layer, wherein

the upper insertion layer includes indium or an indium-tin compound.

2 . A method for manufacturing a vertical transistor, the method comprising:

forming a lower contact material on a substrate;

forming a lower channel material including a metal component and an oxygen component on the lower contact material;

forming a channel material including a metal component and an oxygen component on the lower channel material; and

performing a treatment on the channel material to separate the channel material into an intermediate channel material and an upper channel material on the intermediate channel material forming a lower contact, a lower channel layer, an intermediate channel layer, and an upper channel layer by etching the lower contact material, the lower channel material, the intermediate channel material, and the upper channel material after performing the treatment;

forming an upper barrier layer on the upper channel layer;

forming an upper contact on the upper barrier layer; and

forming an upper insertion layer between the upper channel layer and the upper barrier layer, wherein

the upper insertion layer includes indium or an indium-tin compound.