Semiconductor device

1 . A semiconductor device, comprising

a semiconductor layer including an element region in which an element structure is formed and a termination region located around the element region, wherein

the semiconductor layer located in the termination region includes:

a drift region of a first conductivity;

a plurality of lower guard rings of a second conductivity provided in a first depth range surrounded by the drift region; and

a plurality of upper guard rings of the second conductivity provided in a second depth range different from the first depth range and surrounded by the drift region,

the plurality of lower guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along a predetermined direction connecting the element region and the termination region,

the plurality of upper guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along the predetermined direction,

each of the plurality of lower guard rings has a lower inner peripheral surface facing the element region and a lower outer peripheral surface opposite to the lower inner peripheral surface,

each of the plurality of upper guard rings has an upper inner peripheral surface facing the element region and an upper outer peripheral surface opposite to the upper inner peripheral surface,

an upper portion of the first depth range overlaps a lower portion of the second depth range within a third depth range,

the lower inner peripheral surface of each of the plurality of lower guard rings is offset to one side in the predetermined direction with respect to the upper inner peripheral surface of a corresponding one of the plurality of upper guard rings,

the lower outer peripheral surface of each of the plurality of lower guard rings is offset to the one side in the predetermined direction with respect to the upper outer peripheral surface of a corresponding one of the plurality of upper guard rings, and

a center line of each of the plurality of lower guard rings extends in parallel with and not to intersect a center line of a corresponding one of the plurality of upper guard rings in a plan view of the semiconductor layer.

2 . The semiconductor device according to claim 1 , wherein a minimum interval between the lower guard ring and the upper guard ring adjacent to each other in the predetermined direction increases in order toward the termination region in the predetermined direction.

3 . The semiconductor device according to claim 1 , wherein

the lower inner peripheral surface of each of the plurality of lower guard rings is offset toward the element region in the predetermined direction, relative to the upper inner peripheral surface of a corresponding one of the plurality of upper guard rings, and

the lower outer peripheral surface of each of the plurality of lower guard rings is offset toward the element region in the predetermined direction, relative to the upper outer peripheral surface of a corresponding one of the plurality of upper guard rings.

4 . The semiconductor device according to claim 1 , wherein

the drift region includes:

a low concentration drift region; and

a high concentration drift region having an impurity concentration of the first conductivity higher than that of the low concentration drift region, wherein

the high concentration drift region is provided at an upper side of the low concentration drift region, and

the high concentration drift region is disposed at least between the upper guard rings adjacent to each other in the predetermined direction.

5 . The semiconductor device according to claim 4 , wherein the high concentration drift region is disposed between the lower guard rings adjacent to each other in the predetermined direction.

6 . The semiconductor device according to claim 5 , wherein

the high concentration drift region includes a lower layer, an intermediate layer, and an upper layer,

the intermediate layer has an impurity concentration of the first conductivity lower than that of the lower layer and the upper layer, and

the intermediate layer is located so as to include a depth range in which the first depth range and the second depth range overlap each other.

7 . The semiconductor device according to claim 1 , wherein the semiconductor layer is silicon carbide.

8 . The semiconductor device according to claim 1 , wherein a width of each of the lower guard rings between the lower inner peripheral surface and the lower outer peripheral surface in the predetermined direction is same as a width of each of the upper guard rings between the upper inner peripheral surface and the upper outer peripheral surface in the predetermined direction.

9 . The semiconductor device according to claim 1 , wherein the second depth range is located away from an upper surface ( 10 A) of the semiconductor layer.

10 . A semiconductor device, comprising

a semiconductor layer including an element region in which an element structure is formed and a termination region located around the element region, wherein

the semiconductor layer located in the termination region includes:

a drift region of a first conductivity;

a plurality of lower guard rings of a second conductivity provided in a first depth range surrounded by the drift region; and

a plurality of upper guard rings of the second conductivity provided in a second depth range different from the first depth range and surrounded by the drift region,

the plurality of lower guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along a predetermined direction connecting the element region and the termination region,

the plurality of upper guard rings extend around the element region in a plan view of the semiconductor layer, and are spaced from each other along the predetermined direction,

each of the plurality of lower guard rings has a lower inner peripheral surface facing the element region and a lower outer peripheral surface opposite to the lower inner peripheral surface,

each of the plurality of upper guard rings has an upper inner peripheral surface facing the element region and an upper outer peripheral surface opposite to the upper inner peripheral surface,

an upper portion of each of the plurality of lower guard rings overlaps a lower portion of a corresponding one of the plurality of upper guard rings,

the lower inner peripheral surface of each of the plurality of lower guard rings is offset to one side in the predetermined direction with respect to the upper inner peripheral surface of a corresponding one of the plurality of upper guard rings,

the lower outer peripheral surface of each of the plurality of lower guard rings is offset to the one side in the predetermined direction with respect to the upper outer peripheral surface of a corresponding one of the plurality of upper guard rings, and

a center line of each of the plurality of lower guard rings extends in parallel with and not to intersect a center line of a corresponding one of the plurality of upper guard rings in a plan view of the semiconductor layer,

wherein the drift region includes:

a low concentration drift region; and

a high concentration drift region having an impurity concentration of the first conductivity higher than that of the low concentration drift region, wherein

the high concentration drift region is provided at an upper side of the low concentration drift region, and

the high concentration drift region is disposed at least between the upper guard rings adjacent to each other in the predetermined direction,

wherein the high concentration drift region is disposed between the lower guard rings adjacent to each other in the predetermined direction,

wherein

the high concentration drift region includes a lower layer, an intermediate layer, and an upper layer,

the intermediate layer has an impurity concentration of the first conductivity lower than that of the lower layer and the upper layer, and

the intermediate layer is located so as to include a depth range in which the first depth range and the second depth range overlap each other.