Field-effect transistors with self-aligned p-shield contacts
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a first doped region, a second doped region, a third doped region, and a trench that includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall. The first doped region is disposed adjacent to the first sidewall of the trench, the second doped region is disposed adjacent to the second sidewall of the trench, the third doped region is disposed adjacent to the trench bottom of the trench. The third doped region connects the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a conductivity type. The structure further comprises a gate structure in the trench.
1 . A structure for a field-effect transistor, the structure comprising:
a semiconductor substrate including a first doped region, a second doped region, a third doped region, and a first trench that includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall, the first doped region adjacent to the first sidewall of the first trench, the second doped region adjacent to the second sidewall of the first trench, the third doped region adjacent to the trench bottom of the first trench, the third doped region connecting the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a first conductivity type;
a first gate structure in the first trench, the first gate structure comprising a first portion of a gate dielectric layer and a first portion of a gate conductor layer in the first trench; and
a dielectric layer including a first portion on the first portion of the gate conductor layer and a second portion on the semiconductor substrate,
wherein the first portion of the dielectric layer is thicker than the second portion of the dielectric layer.
2 . The structure of claim 1 wherein the first trench has a third sidewall between the first sidewall and the second sidewall, and the semiconductor substrate further includes a second trench having a sidewall adjacent to the third sidewall of the first trench.
3 . The structure of claim 2 wherein the semiconductor substrate includes a channel region between the third sidewall of the first trench and the sidewall of the second trench.
4 . The structure of claim 1 wherein the first conductivity type is p-type.
5 . The structure of claim 1 wherein the semiconductor substrate includes a top surface and a fourth doped region between the trench bottom and the top surface, the first trench extends through the fourth doped region, and the fourth doped region has the first conductivity type.
6 . The structure of claim 1 wherein the semiconductor substrate includes a top surface and a fourth doped region between the trench bottom and the top surface, the first trench extends through the fourth doped region, the fourth doped region has a second conductivity type opposite to the first conductivity type, and further comprising:
an electrode; and
a silicide layer on the top surface of the semiconductor substrate,
wherein the silicide layer couples the electrode to the fourth doped region.
7 . The structure of claim 6 wherein the semiconductor substrate includes a fifth doped region in the fourth doped region, the fifth doped region has the first conductivity type, and the silicide layer couples the electrode to the fifth doped region.
8 . The structure of claim 1 wherein the semiconductor substrate comprises a wide bandgap semiconductor material.
9 . The structure of claim 8 wherein the wide bandgap semiconductor material comprises silicon carbide.
10 . The structure of claim 1 wherein the first trench and the first gate structure are disposed between the first doped region and the second doped region.
11 . The structure of claim 1 wherein the third doped region extends beneath the trench bottom of the first trench from the first doped region to the second doped region.
12 . The structure of claim 1 wherein the first trench has a first length dimension, the semiconductor substrate further includes a second trench having a second length dimension, and the first trench is longitudinally aligned with the second trench.
13 . The structure of claim 12 wherein the first sidewall of the first trench is spaced along the first length dimension from the second sidewall of the first trench.
14 . The structure of claim 12 wherein the second trench has a sidewall adjacent to the first sidewall of the first trench, the semiconductor substrate includes a fourth doped region adjacent to the sidewall of the second trench, and the fourth doped region has the first conductivity type.
15 . The structure of claim 14 further comprising:
a second gate structure in the second trench,
wherein the second gate structure comprises a second portion of the gate conductor layer, and the first gate structure and the second gate structure are connected by a third portion of the gate conductor layer to define a gate finger.
16 . The structure of claim 15 wherein the first portion of the gate conductor layer of the first gate structure includes a first recess, and the second portion of the gate conductor layer of the second gate structure includes a second recess.
17 . The structure of claim 15 wherein the gate conductor layer comprises doped silicon, and the dielectric layer comprises silicon dioxide.
18 . The structure of claim 1 wherein the semiconductor substrate includes a top surface, the first sidewall and the second sidewall extend from the trench bottom to the top surface, and the first doped region and the second doped region extend from the third doped region to the top surface.
19 . A method of forming a structure for a field-effect transistor, the method comprising:
forming a first trench in a semiconductor substrate, wherein the first trench includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall;
forming a first doped region adjacent to the first sidewall of the first trench;
forming a second doped region adjacent to the second sidewall of the first trench;
forming a third doped region adjacent to the trench bottom of the first trench, wherein the third doped region connects the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a first conductivity type;
forming a first gate structure in the first trench, wherein the first gate structure comprises a portion of a gate dielectric layer and a portion of a gate conductor layer in the first trench; and
forming a dielectric layer including a first portion on the first gate structure and a second portion on the semiconductor substrate,
wherein the first portion of the dielectric layer is thicker than the second portion of the dielectric layer.
20 . The method of claim 19 wherein the semiconductor substrate further includes a second trench, a second gate structure is disposed in the second trench, the first gate structure and the second gate structure comprise doped silicon, the first gate structure and the second gate structure are connected by a portion of the doped silicon to define a gate finger, and further comprising:
oxidizing the doped silicon to form the dielectric layer on the gate finger.