Back-end-of-line vertical-transport transistor

1 . A semiconductor structure comprising:

a bottom source drain region arranged above front-end-of-line circuitry;

a gate region disposed above and insulated from the bottom source drain region;

a top source drain region disposed above and insulated from the gate region;

a channel region adjacent to the gate region and extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region; and

a gate dielectric separating the gate region from the channel region, wherein the channel region wraps around and directly contacts a bottom surface, a sidewall, and a top surface of the gate dielectric.

2 . The semiconductor structure according to claim 1 , further comprising:

a bottom contact partially embedded into the bottom source drain region;

a top contact partially embedded into the top source drain region; and

a gate contact partially embedded into the gate region.

3 . The semiconductor structure according to claim 1 , further comprising:

a bottom gate spacer between and physically separating the gate region from the bottom source drain region; and

a top gate spacer between and physically separating the gate region from the top source drain region.

4 . The semiconductor structure according to claim 1 , wherein a width of the bottom source drain region is greater than a width of the gate region, and wherein the width of the gate region is greater than a width of the top source drain region.

5 . The semiconductor structure according to claim 1 , wherein a height of the gate dielectric is substantially equal to a height of the gate region.

6 . The semiconductor structure according to claim 1 , wherein the channel region comprises indium oxide, indium tin oxide, indium gallium zinc oxide, indium aluminum zinc oxide, amorphous silicon, polysilicon, or some combination thereof.

7 . A semiconductor structure comprising:

two or more bottom source drain regions arranged above front-end-of-line circuitry and electrically isolated from one another;

a single gate region disposed above and insulated from the two or more bottom source drain regions;

a trench isolator between and physically separating a first portion of the single gate region from a second portion of the single gate region, wherein sidewalls of the trench isolator directly contact a sidewall of the first portion of the single gate region and a sidewall of the second portion of the single gate region;

two or more top source drain regions disposed above and insulated from the single gate region and electrically isolated from one another; and

two or more channel regions adjacent to the single gate region, each channel region extending vertically from a top surface of one of the two or more bottom source drain regions to a bottom surface of one of the two or more top source drain regions.

8 . The semiconductor structure according to claim 7 , further comprising:

two or more bottom contacts, wherein each of the two or more bottom contacts is partially embedded into one of the two or more bottom source drain regions;

two or more top contacts, wherein each of the two or more top contacts is partially embedded into one of the two or more top source drain regions;

a first gate contact partially embedded into the first portion of the single gate region; and

a second gate contact partially embedded into the second portion of the single gate region.

9 . The semiconductor structure according to claim 7 , further comprising:

a first gate dielectric separating the first portion of the single gate region from a first channel of the two or more channel regions, wherein a height of the first gate dielectric is substantially equal to a height of the two or more channel regions measured from the top surface of the two or more bottom source drain regions to the bottom surface of the two or more top source drain regions; and

a second gate dielectric separating the second portion of the single gate region from a second channel of the two or more channel regions, wherein a height of the second gate dielectric is substantially equal to the height of the two or more channel regions measured from the top surface of the two or more bottom source drain regions to the bottom surface of the two or more top source drain regions.

10 . The semiconductor structure according to claim 7 , wherein a width of one of the two or more bottom source drain regions is greater than a width of one of the two or more top source drain regions.

11 . The semiconductor structure according to claim 7 , further comprising:

a bottom gate spacer directly below the single gate region insulating the single gate region from the two or more bottom source drain regions; and

a top gate spacer above the single gate region insulating the single gate region from the two or more top source drain regions.

12 . The semiconductor structure according to claim 7 , further comprising:

a bottom gate spacer directly below the single gate region insulating the single gate region from the two or more bottom source drain regions; and

a top gate spacer above the single gate region insulating the single gate region from the two or more top source drain regions,

wherein a combined height of the bottom gate spacer, the single gate region, and the top gate spacer is equal to a height of the two or more channel regions.

13 . The semiconductor structure according to claim 7 , wherein the two or more channel regions comprises indium oxide, indium tin oxide, indium gallium zinc oxide, indium aluminum zinc oxide, amorphous silicon, polysilicon, or some combination thereof.

14 . The semiconductor structure according to claim 7 , wherein a bottommost surface of the trench isolator is below bottommost surfaces of both the first portion of the single gate region and the second portion of the single gate region, and wherein a topmost surface of the trench isolator is substantially flush with topmost surfaces of two or more bottom contacts, two or more top contacts, a first gate contact, and a second gate contact.

15 . A semiconductor structure comprising:

a bottom source drain region arranged above front-end-of-line circuitry;

a single gate region disposed above and insulated from the bottom source drain region;

a top source drain region disposed above and insulated from the single gate region;

a channel region surrounding the single gate region, the channel region extending vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region;

a bottom gate spacer directly below the single gate region insulating the single gate region from the bottom source drain region; and

a top gate spacer above the single gate region insulating the single gate region from the top source drain region,

wherein the bottom gate spacer, the single gate region, and the top gate spacer have substantially equal widths.

16 . The semiconductor structure according to claim 15 , further comprising:

gate dielectric separating the single gate region from the channel region, each of the gate dielectric extend vertically from a top surface of the bottom source drain region to a bottom surface of the top source drain region.

17 . The semiconductor structure according to claim 15 , wherein a width of the bottom source drain region is greater than a width of the top source drain region.

18 . The semiconductor structure according to claim 15 , wherein a combined height of the bottom gate spacer, the single gate region, and the top gate spacer is equal to a height of the channel region.

19 . The semiconductor structure according to claim 15 , wherein the channel region comprises indium oxide, indium tin oxide, indium gallium zinc oxide, indium aluminum zinc oxide, amorphous silicon, polysilicon, or some combination thereof.

20 . The semiconductor structure according to claim 15 , further comprising:

a dielectric layer surrounding and electrically insulating the channel region from adjacent structures embedded in the dielectric layer.